The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-39
ID121610 Non-Confidential
3.5 General data processing instructions
Table 3-8 shows the data processing instructions:
Table 3-8 Data processing instructions
Mnemonic Brief description See
ADC
Add with Carry ADD, ADC, SUB, SBC, and RSB on page 3-41
ADD
Add ADD, ADC, SUB, SBC, and RSB on page 3-41
ADDW
Add ADD, ADC, SUB, SBC, and RSB on page 3-41
AND
Logical AND AND, ORR, EOR, BIC, and ORN on page 3-44
ASR
Arithmetic Shift Right ASR, LSL, LSR, ROR, and RRX on page 3-46
BIC
Bit Clear AND, ORR, EOR, BIC, and ORN on page 3-44
CLZ
Count leading zeros CLZ on page 3-48
CMN
Compare Negative CMP and CMN on page 3-49
CMP
Compare CMP and CMN on page 3-49
EOR
Exclusive OR AND, ORR, EOR, BIC, and ORN on page 3-44
LSL
Logical Shift Left ASR, LSL, LSR, ROR, and RRX on page 3-46
LSR
Logical Shift Right ASR, LSL, LSR, ROR, and RRX on page 3-46
MOV
Move MOV and MVN on page 3-50
MOVT
Move Top MOVT on page 3-52
MOVW
Move 16-bit constant MOV and MVN on page 3-50
MVN
Move NOT MOV and MVN on page 3-50
ORN
Logical OR NOT AND, ORR, EOR, BIC, and ORN on page 3-44
ORR
Logical OR AND, ORR, EOR, BIC, and ORN on page 3-44
RBIT
Reverse Bits REV, REV16, REVSH, and RBIT on page 3-53
REV
Reverse byte order in a word REV, REV16, REVSH, and RBIT on page 3-53
REV16
Reverse byte order in each halfword REV, REV16, REVSH, and RBIT on page 3-53
REVSH
Reverse byte order in bottom halfword and sign extend REV, REV16, REVSH, and RBIT on page 3-53
ROR
Rotate Right ASR, LSL, LSR, ROR, and RRX on page 3-46
RRX
Rotate Right with Extend ASR, LSL, LSR, ROR, and RRX on page 3-46
RSB
Reverse Subtract ADD, ADC, SUB, SBC, and RSB on page 3-41
SADD16
Signed Add 16 SADD16 and SADD8 on page 3-54
SADD8
Signed Add 8 SADD16 and SADD8 on page 3-54
SASX
Signed Add and Subtract with Exchange SASX and SSAX on page 3-60
SSAX
Signed Subtract and Add with Exchange SASX and SSAX on page 3-60
SBC
Subtract with Carry ADD, ADC, SUB, SBC, and RSB on page 3-41
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