Cortex-M4 Peripherals
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 4-20
ID121610 Non-Confidential
The bit assignments are:
DIV_0_TRP
Reserved
UNALIGN_TRP
NONBASETHRDENA
USERSETMPEND
BFHFNMIGN
STKALIGN
Reserved
31 10 9 8 7 5 4 3 2 1 0
Reserved
Table 4-20 CCR bit assignments
Bits Name Function
[31:10] - Reserved.
[9] STKALIGN Indicates stack alignment on exception entry:
0 = 4-byte aligned
1 = 8-byte aligned.
On exception entry, the processor uses bit[9] of the stacked PSR to indicate the
stack alignment. On return from the exception it uses this stacked bit to restore
the correct stack alignment.
[8] BFHFNMIGN Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load
and store instructions. This applies to the hard fault, NMI, and FAULTMASK
escalated handlers:
0 = data bus faults caused by load and store instructions cause a lock-up
1 = handlers running at priority -1 and -2 ignore data bus faults caused by load
and store instructions.
Set this bit to 1 only when the handler and its data are in absolutely safe memory.
The normal use of this bit is to probe system devices and bridges to detect control
path problems and fix them.
[7:5] - Reserved.
[4] DIV_0_TRP Enables faulting or halting when the processor executes an
SDIV
or
UDIV
instruction with a divisor of 0:
0 = do not trap divide by 0
1 = trap divide by 0.
When this bit is set to 0, a divide by zero returns a quotient of 0.
[3] UNALIGN_TRP Enables unaligned access traps:
0 = do not trap unaligned halfword and word accesses
1 = trap unaligned halfword and word accesses.
If this bit is set to 1, an unaligned access generates a UsageFault.
Unaligned
LDM
,
STM
,
LDRD
, and
STRD
instructions always fault irrespective of
whether UNALIGN_TRP is set to 1.
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