ARM Cortex-M4 - Page 233

Cortex-M4 Peripherals
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 4-17
ID121610 Non-Confidential
The bit assignments are:
On read: VECTKEYSTAT
On write: VECTKEY
31 16 15 14 11 10 8 7 3 2 1 0
Reserved Reserved
ENDIANNESS PRIGROUP SYSRESETREQ
VECTCLRACTIVE
VECTRESET
Reserved for Debug use
Table 4-17 AIRCR bit assignments
Bits Name Type Function
[31:16] Write: VECTKEYSTAT
Read: VECTKEY
RW Register key:
Reads as
0xFA05
On writes, write 0x5FA to VECTKEY, otherwise the write is ignored.
[15] ENDIANNESS RO Data endianness bit is implementation defined:
0 = Little-endian
1 = Big-endian.
[14:11] - - Reserved.
[10:8] PRIGROUP R/W Interrupt priority grouping field is implementation defined. This field
determines the split of group priority from subpriority, see Binary point on
page 4-18.
[7:3] - - Reserved.
[2] SYSRESETREQ WO System reset request bit is implementation defined:
0 = no system reset request
1 = asserts a signal to the outer system that requests a reset.
This is intended to force a large system reset of all major components
except for debug.
This bit reads as 0.
See you vendor documentation for more information about the use of this
signal in your implementation.
[1] VECTCLRACTIVE WO Reserved for Debug use. This bit reads as 0. When writing to the register
you must write 0 to this bit, otherwise behavior is Unpredictable.
[0] VECTRESET WO Reserved for Debug use. This bit reads as 0. When writing to the register
you must write 0 to this bit, otherwise behavior is Unpredictable.