COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 20 www.cobham.com/gaisler
GR712RC
2.3 2013-05-13 1.2
1.7.8
2
3.2
5.1
5.8.1
5.10.3
5.14.2
6.2
11.3
12.3
14.3
15.3
16.3.4
16.6
16.8
17.7
25.1
25.3
Memory controller maximum SRAM/SDRAM size supported
Added “LEON3FT Cache Controller: Incorrect Bus Access
After Power-Down” errata
Behavior of switch matrix output when CAN core is enabled
SpaceWire clock max frequency and startup bandwidth
Added maximum capacities for SRAM and SDRAM
Units and SDRAM + RS EDAC bus width
EDAC Error reporting behavior clarifications
SDRAM Column Size clarification
On-chip memory performance statistics update
Register layout fixes for General Purpose Timer
Register layout fixes for Latching General Purpose Timer
Documented interrupt mask register
Clarified scaler behavior with respect to clocking
Removed unsupported tick-in signal reference
RMAP support only on GRSPW2-0 and GRSPW2-1
SpaceWire clock max frequency and startup bandwidth
Clarified reset PHY address value
Specified number of slaves and data word length for GRASCS
Documented Output Enable bit
Documented TMD bit
Fixed ETR scale register width
2.2 2013-02-20 1.2, 1.3, 1.4,
1.5, 2, 3.6, 3.9,
8.3, 13.2, 19,
20, 28.2
1.3
1.3, 18.3
1.7.2
1.7.7, 5.1, 5.10
3.3, 21.3
3.8
3.8
4.2.12, 4.6.1,
4.6.3
5.8
15.3
Obsolete proprietary function removed


APB addresses corrected
CANOC addresses corrected
CANOC errata updated
Note on EDAC usage with 8-bit wide memory introduced
Mil-Std-1553B clocking clarified
DLLBPN polarity corrected
Delay line explained, figure added
MMU and cache handling clarified
SDRAM example programming clarified
UART baud rate generation clarified
TABLE 4. Revision history
Issue Date Sections Description

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English