Freescale Semiconductor FlexRay MFR4310

Memory Map65

Table 3-3. Flexray Memory Map65

Register Descriptions68

Table 3-4. Register Access Conventions68

Table 3-5. Additional Register Reset Conditions69

Table 3-6. Register Write Access Restrictions69

Figure 3-2. Module Version Register (MVR)70

Figure 3-3. Module Configuration Register (MCR)70

Table 3-7. MVR Field Descriptions70

Table 3-8. MCR Field Descriptions71

Table 3-9. Flexray Channel Selection71

Figure 3-4. Strobe Signal Control Register (STBSCR)72

Table 3-10. Flexray Channel Bit Rate Selection72

Table 3-11. STBSCR Field Descriptions73

Table 3-12. Strobe Signal Mapping73

Figure 3-5. Message Buffer Data Size Register (MBDSR)75

Figure 3-6. Message Buffer Segment Size and Utilization Register (MBSSUTR)76

Table 3-13. MBDSR Field Descriptions76

Table 3-14. MBSSUTR Field Descriptions76

Figure 3-7. Protocol Operation Control Register (POCR)77

Table 3-15. POCR Field Descriptions77

Figure 3-8. Global Interrupt Flag and Enable Register (GIFER)78

Table 3-16. GIFER Field Descriptions79

Figure 3-9. Protocol Interrupt Flag Register 0 (PIFR0)81

Table 3-17. PIFR0 Field Descriptions81

Figure 3-10. Protocol Interrupt Flag Register 1 (PIFR1)83

Table 3-18. PIFR1 Field Descriptions83

Figure 3-11. Protocol Interrupt Enable Register 0 (PIER0)84

Table 3-19. PIER0 Field Descriptions84

Figure 3-12. Protocol Interrupt Enable Register 1 (PIER1)85

Table 3-20. PIER1 Field Descriptions85

Figure 3-13. CHI Error Flag Register (CHIERFR)86

Table 3-21. CHIERFR Field Descriptions86

Figure 3-14. Message Buffer Interrupt Vector Register (MBIVEC)88

Table 3-22. MBIVEC Field Descriptions88

Figure 3-15. Channel a Status Error Counter Register (CASERCR)89

Figure 3-16. Channel B Status Error Counter Register (CBSERCR)89

Table 3-23. CASERCR Field Descriptions89

Table 3-24. CBSERCR Field Descriptions89

Figure 3-17. Protocol Status Register 0 (PSR0)90

Table 3-25. PSR0 Field Descriptions90

Figure 3-18. Protocol Status Register 1 (PSR1)91

Figure 3-19. Protocol Status Register 2 (PSR2)92

Table 3-26. PSR1 Field Descriptions92

Table 3-27. PSR2 Field Descriptions93

Figure 3-20. Protocol Status Register 3 (PSR3)94

Table 3-28. PSR3 Field Descriptions95

Figure 3-21. Macrotick Counter Register (MTCTR)96

Figure 3-22. Cycle Counter Register (CYCTR)96

Table 3-29. MTCTR Field Descriptions96

Table 3-30. CYCTR Field Descriptions96

Figure 3-23. Slot Counter Channel a Register (SLTCTAR)97

Figure 3-24. Slot Counter Channel B Register (SLTCTBR)97

Figure 3-25. Rate Correction Value Register (RTCORVR)97

Table 3-31. SLTCTAR Field Descriptions97

Table 3-32. SLTCTBR Field Descriptions97

Figure 3-26. Offset Correction Value Register (OFCORVR)98

Figure 3-27. Combined Interrupt Flag Register (CIFRR)98

Table 3-33. RTCORVR Field Descriptions98

Table 3-34. OFCORVR Field Descriptions98

Table 3-35. CIFRR Field Descriptions99

Figure 3-28. Sync Frame Counter Register (SFCNTR)100

Figure 3-29. Sync Frame Table Offset Register (SFTOR)100

Table 3-36. SFCNTR Field Descriptions100

Figure 3-30. Sync Frame Table Configuration, Control, Status Register (SFTCCSR)101

Table 3-37. SFTOR Field Description101

Table 3-38. SFTCCSR Field Descriptions101

Figure 3-31. Sync Frame ID Rejection Filter Register (SFIDRFR)102

Table 3-39. SFIDRFR Field Descriptions102

Figure 3-32. Sync Frame ID Acceptance Filter Value Register (SFIDAFVR)103

Figure 3-33. Sync Frame ID Acceptance Filter Mask Register (SFIDAFMR)103

Figure 3-34. Network Management Vector Registers (NMVR0-NMVR5)103

Table 3-40. SFIDAFVR Field Descriptions103

Table 3-41. SFIDAFMR Field Descriptions103

Table 3-42. NMVR[0:5] Field Descriptions104

Table 3-43. Mapping of Nmvrn to the Received Payload Bytes Nmvn104

Table 3-44. NMVLR Field Descriptions104

Figure 3-36. Timer Configuration and Control Register (TICCR)105

Table 3-45. TICCR Field Descriptions105

Figure 3-37. Timer 1 Cycle Set Register (TI1CYSR)106

Figure 3-38. Timer 1 Macrotick Offset Register (TI1MTOR)106

Table 3-46. TI1CYSR Field Descriptions106

Table 3-47. TI1MTOR Field Descriptions106

Figure 3-39. Timer 2 Configuration Register 0 (TI2CR0)107

Figure 3-40. Timer 2 Configuration Register 1 (TI2CR1)107

Table 3-48. TI2CR0 Field Descriptions107

Figure 3-41. Slot Status Selection Register (SSSR)108

Table 3-49. TI2CR1 Field Descriptions108

Figure 3-42. Slot Status Counter Condition Register (SSCCR)109

Table 3-50. SSSR Field Descriptions109

Table 3-51. Mapping between Sssrn and Ssrn109

Table 3-52. SSCCR Field Descriptions110

Table 3-53. Mapping between Internal Ssccrn and Sscrn110

Figure 3-43. Slot Status Registers (SSR0-SSR7)111

Table 3-54. SSR0-SSR7 Field Descriptions111

Figure 3-44. Slow Status Counter Registers (SSCR0-SSCR3)112

Figure 3-45. MTS a Configuration Register (MTSACFR)113

Figure 3-46. MTS B Configuration Register (MTSBCFR)113

Table 3-55. SSCR0-SSCR3 Field Descriptions113

Table 3-56. MTSACFR Field Descriptions113

Figure 3-47. Receive Shadow Buffer Index Register (RSBIR)114

Table 3-57. MTSBCFR Field Descriptions114

Table 3-58. RSBIR Field Descriptions114

Figure 3-48. Receive FIFO Selection Register (RFSR)115

Figure 3-49. Receive FIFO Start Index Register (RFSIR)115

Table 3-59. SEL Controlled Receiver FIFO Registers115

Table 3-60. RFSR Field Descriptions115

Table 3-61. RFSIR Field Descriptions115

Figure 3-50. Receive FIFO Depth and Size Register (RFDSR)116

Figure 3-51. Receive FIFO a Read Index Register (RFARIR)116

Table 3-62. RFDSR Field Descriptions116

Table 3-63. RFARIR Field Descriptions116

Figure 3-52. Receive FIFO B Read Index Register (RFBRIR)117

Figure 3-53. Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR)117

Table 3-64. RFBRIR Field Descriptions117

Table 3-65. RFMIDAFVR Field Descriptions117

Figure 3-54. Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR)118

Figure 3-55. Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR)118

Figure 3-56. Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR)118

Table 3-66. RFMIAFMR Field Descriptions118

Table 3-67. RFFIDRFVR Field Descriptions118

Figure 3-57. Receive FIFO Range Filter Configuration Register (RFRFCFR)119

Figure 3-58. Receive FIFO Range Filter Control Register (RFRFCTR)119

Table 3-68. RFFIDRFMR Field Descriptions119

Table 3-69. RFRFCFR Field Descriptions119

Figure 3-59. Last Dynamic Slot Channel a Register (LDTXSLAR)120

Table 3-70. RFRFCTR Field Descriptions120

Table 3-71. LDTXSLAR Field Descriptions120

Figure 3-60. Last Dynamic Slot Channel B Register (LDTXSLBR)121

Table 3-72. LDTXSLBR Field Descriptions121

Table 3-73. Protocol Configuration Register Fields121

Figure 3-61. Protocol Configuration Register 0 (PCR0)123

Figure 3-62. Protocol Configuration Register 1 (PCR1)123

Figure 3-63. Protocol Configuration Register 2 (PCR2)123

Table 3-74. Wakeup Channel Selection123

Figure 3-64. Protocol Configuration Register 3 (PCR3)124

Figure 3-65. Protocol Configuration Register 4 (PCR4)124

Figure 3-66. Protocol Configuration Register 5 (PCR5)124

Figure 3-67. Protocol Configuration Register 6 (PCR6)124

Figure 3-68. Protocol Configuration Register 7 (PCR7)124

Figure 3-69. Protocol Configuration Register 8 (PCR8)125

Figure 3-70. Protocol Configuration Register 9 (PCR9)125

Figure 3-71. Protocol Configuration Register 10 (PCR10)125

Figure 3-72. Protocol Configuration Register 11 (PCR11)125

Figure 3-73. Protocol Configuration Register 12 (PCR12)126

Figure 3-74. Protocol Configuration Register 13 (PCR13)126

Figure 3-75. Protocol Configuration Register 14 (PCR14)126

Figure 3-76. Protocol Configuration Register 15 (PCR15)126

Figure 3-77. Protocol Configuration Register 16 (PCR16)126

Figure 3-78. Protocol Configuration Register 17 (PCR17)127

Figure 3-79. Protocol Configuration Register 18 (PCR18)127

Figure 3-80. Protocol Configuration Register 19 (PCR19)127

Figure 3-81. Protocol Configuration Register 20 (PCR20)127

Figure 3-82. Protocol Configuration Register 21 (PCR21)127

Figure 3-83. Protocol Configuration Register 22 (PCR22)128

Figure 3-84. Protocol Configuration Register 23 (PCR23)128

Figure 3-85. Protocol Configuration Register 24 (PCR24)128

Figure 3-86. Protocol Configuration Register 25 (PCR25)128

Figure 3-87. Protocol Configuration Register 26 (PCR26)128

Figure 3-88. Protocol Configuration Register 27 (PCR27)129

Figure 3-89. Protocol Configuration Register 28 (PCR28)129

Figure 3-90. Protocol Configuration Register 29 (PCR29)129

Figure 3-91. Protocol Configuration Register 30 (PCR30)129

Figure 3-92. Message Buffer Configuration, Control, Status Registers (Mbccsrn)130

Table 3-75. Mbccsrn Field Descriptions130

Figure 3-93. Message Buffer Cycle Counter Filter Registers (Mbccfrn)132

Table 3-76. Mbccfrn Field Descriptions132

Table 3-77. Channel Assignment Description132

Figure 3-94. Message Buffer Frame ID Registers (Mbfidrn)133

Figure 3-95. Message Buffer Index Registers (Mbidxrn)133

Table 3-78. Mbfidrn Field Descriptions133

Table 3-79. Mbidxrn Field Descriptions133

Brand	Freescale Semiconductor
Model	FlexRay MFR4310
Category	Controller
Language	English

Freescale Semiconductor FlexRay MFR4310 - User Manual

Table of Contents

Freescale Semiconductor FlexRay MFR4310 Specifications