Freescale Semiconductor FlexRay MFR4310 - VDDOSC, V SSOSC - Regulator Output2 (OSC); Functional Description; REG - Regulator Core; Full-Performance Mode

Dual Output Voltage Regulator (VREG3V3V2)
MFR4310 Reference Manual, Rev. 2
220 Freescale Semiconductor
5.2.3 V
DD2_5
, V
SS2_5
— Regulator Output1 (Core Logic)
Signals V
DD2_5
/V
SS2_5
are the primary outputs of VREG3V3V2 that provide the power supply for the
core logic. These signals are connected to device pins to allow external decoupling capacitors (100
nF…220 nF, X7R ceramic).
In shutdown mode an external supply at V
DD2_5
/V
SS2_5
can replace the voltage regulator.
5.2.4 V
DDOSC
, V
SSOSC
— Regulator Output2 (OSC)
Signals V
DDOSC
/V
SSOSC
are the secondary outputs of VREG3V3V2 that provide the power supply for the
oscillator. These signals are connected to device pins to allow external decoupling capacitors (100 nF…220
nF, X7R ceramic).
In shutdown mode an external supply at V
DDOSC
/V
SSOSC
can replace the voltage regulator.
5.3 Functional Description
Block VREG3V3V2 is a voltage regulator as depicted in Figure 5-1. The regulator functional elements are
the regulator core (REG), a power-on reset module (POR) and a low-voltage reset module (LVR). There
is also the regulator control block (CTRL) which manages the operating modes of VREG3V3V2.
5.3.1 REG — Regulator Core
VREG3V3V2, respectively its regulator core has two parallel, independent regulation loops (REG1 and
REG2) that differ only in the amount of current that can be sourced to the connected loads. Therefore, only
REG1 providing the supply at V
DD2_5
/V
SS2_5
is explained. The principle is also valid for REG2.
The regulator is a linear series regulator with a bandgap reference in its full-performance mode and a
voltage clamp in reduced-power mode. All load currents flow from input V
DDR
to V
SS2_5
or V
SSOSC
, the
reference circuits are connected to V
DDA
and V
SSA
.
5.3.2 Full-performance Mode
In full-performance mode, a fraction of the output voltage (V
DD2_5
) and the bandgap reference voltage are
fed to an operational amplifier. The amplified input voltage difference controls the gate of an output driver.
5.3.3 POR — Power On Reset
This functional block monitors output V
DD2_5
. If V
DD2_5
is below V
PORD
, signal POR is high; if it
exceeds V
PORD
, the signal goes low. The transition to low forces the CPU into the power-on sequence.
Due to its role during chip power-up, this module must be active in all operating modes of VREG3V3V2.