Freescale Semiconductor FlexRay MFR4310 - Functional Description; Reset Generation; Table 6-4. CRG Reset Sources Priorities

Clocks and Reset Generator (CRG)
MFR4310 Reference Manual, Rev. 2
226 Freescale Semiconductor
6.4 Functional Description
6.4.1 Reset Generation
The CRG provides a system reset in any of the following events: power-on, low-voltage, or clock monitor
failure (if enabled) detected, low level detected at the RESET# pin. Entry into reset is asynchronous and
does not require a clock. However, the MFR4310 cannot sequence out of reset in Functional Mode without
a system clock. Table 6-4 depicts reset sources priorities.
The CRG scans, during different periods depending on the origin of the reset source, the interface type, the
AMI clock source and the CLKOUT mode selection pins: IF_SEL[1:0] and CLK_S[1:0].
NOTE
After the CRG has started a reset procedure, it does not abandon it unless a
reset event with more priority is detected. A reset procedure with the same
priority as the currently running one stops the previous procedure and is
executed.
6.4.1.1 Power-on Reset
When the power-on reset signal is asserted the CRG asserts the system reset signal. The CRG
synchronously deasserts the system reset signal approximately 16420 EXTAL/CLK_CC clock periods after
the deassertion of the power-on reset signal.
The CRG resets the DER.CMIE bit to 0, asserts the INT_CC# interrupt line, and sets the power-on reset
interrupt flag, CRSR.PRIF, on the rising edge of the power-on reset signal.
NOTE
The CRG deasserts the INT_CC# signal when the CRSR.PRIF,
CRSR.LVIF, CRSR.CMIF and CRSR.ERIF bits are 0.
Figure 6-3 illustrates the power-on reset situation.
Table 6-4. CRG Reset Sources Priorities
Reset Source Block to Reset Priority
Power-on Reset Whole device High
Low voltage or Clock Monitor Failure (if enabled) Reset Whole device
External Reset Whole device Low