Dual Output Voltage Regulator (VREG3V3V2)
MFR4310 Reference Manual, Rev. 2
Freescale Semiconductor 221
5.3.4 LVR — Low Voltage Reset
Block LVR monitors the primary output voltage V
DD2_5
. If it drops below the assertion level (V
LVRA
)
signal LVR asserts and when rising above the deassertion level (V
LVRD
) signal LVR deasserts again. The
LVR function is available only in full-performance mode.
5.3.5 CTRL — Regulator Control
This part contains digital functionality needed to control the operating modes.
5.4 Resets
This subsection describes how VREG3V3V2 controls the reset of the CC. The reset values of registers and
signals are provided in Section 3.3, “Memory Map and Register Description”. Possible reset sources are
listed in Table 5-2.
5.4.1 Power On Reset
During chip power-up the digital core may not work if its supply voltage V
DD2_5
is below the POR
deassertion level (V
PORD
). Therefore, signal POR, which forces the other blocks of the device into reset,
is kept high until V
DD2_5
exceeds V
PORD
. Then POR becomes low and the reset generator of the device
continues the start-up sequence.
5.4.2 Low Voltage Reset
For information on low-voltage reset see Section 5.3.4, “LVR — Low Voltage Reset”.
Table 5-2. VREG3V3V2 — Reset Sources
Reset Source Local Enable
Power-on reset Always active
Low-voltage reset Always active
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