Electrical Characteristics
MFR4310 Reference Manual, Rev. 2
250 Freescale Semiconductor
A.3.2 Oscillator
The device features an internal Pierce oscillator with a clock monitor. A clock monitor failure is asserted
if the clock signal is below the Clock Monitor Assert Frequency, f
CMAF
.
A.4 Asynchronous Memory Interface Timing
The CC AMI Interface read/write timing diagram is shown in the following figures.
• Writing to the device is accomplished when Chip Enable (CE#) and Write Enable (WE#) inputs
are LOW (asserted).
• Reading from the device is accomplished when Chip Enable (CE#) and Output Enable (OE#) are
LOW (asserted) while the Write Enable (WE#) is HIGH (deasserted).
• The input/output pins D[15:0] are in a high-impedance state when the device is not selected (CE#
is HIGH), the outputs are disabled (OE# HIGH) or during a write operation (CE# LOW, and WE#
LOW).
Table A-12. Oscillator Characteristics
Conditions are shown in Ta bl e A -4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 C Crystal oscillator range (Pierce)
1, 2
1
Depending on the crystal, a damping series resistor might be necessary.
2
Input clock frequency applied to EXTAL/CLK_CC.
f
OSC
0.5 - 40 MHz
2 P Startup Current i
OSC
100 - - μA
4 P Clock monitor assert frequency f
CMAF
50 100 200 kHz
5 P External square wave input frequency f
EXT
0.5 - 50 MHz
6 D External square wave pulse width low t
EXTL
9.5 - - ns
7 D External square wave pulse width high t
EXTH
9.5 - - ns
8 D External square wave rise time t
EXTR
--1ns
9 D External square wave fall time t
EXTF
--1ns
10 D Input Capacitance (EXTAL, XTAL pins) C
IN
-7-pF
11 C DC Operating Bias in Pierce mode on EXTAL Pin V
DCBIAS
-2.5-V
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