Device Overview
MFR4310 Reference Manual, Rev. 2
Freescale Semiconductor 57
• Internal power-on and low-voltage resets provided by the internal voltage regulator (refer to
Chapter 6, “Clocks and Reset Generator (CRG)” and Chapter 5, “Dual Output Voltage Regulator
(VREG3V3V2)” for more information).
• Internal clock monitor failure reset (see Chapter 7, “Oscillator (OSCV2)”).
When a reset occurs, MFR4310 registers and control bits are changed to known startup states. Refer to the
respective module chapters for information on the different kinds of resets and for register reset states.
2.8.1.1 I/O Pin States After Reset
Refer to Table 2-3 for the configuration of the MFR4310 pins out of reset.
2.8.2 Interrupt Sources
All possible MFR4310 internal interrupt sources are combined and provided to the host by means of one
available interrupt line, INT_CC#. Refer to Section 3.4.19, “Interrupt Support” and Section 6.3.2, “Clock
and Reset Status Register (CRSR)” for more information on available interrupt sources. The type of
interrupt is level sensitive.
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