Freescale Semiconductor FlexRay MFR4310 - Page 14

MFR4310 Reference Manual, Rev. 2
14 Freescale Semiconductor
Figure Number Title Page
Figure 3-22. Cycle Counter Register (CYCTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 3-23. Slot Counter Channel A Register (SLTCTAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 3-24. Slot Counter Channel B Register (SLTCTBR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 3-25. Rate Correction Value Register (RTCORVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 3-26. Offset Correction Value Register (OFCORVR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 3-27. Combined Interrupt Flag Register (CIFRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 3-28. Sync Frame Counter Register (SFCNTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 3-29. Sync Frame Table Offset Register (SFTOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 3-30. Sync Frame Table Configuration, Control, Status Register (SFTCCSR). . . . . . . . . . . . 101
Figure 3-31. Sync Frame ID Rejection Filter Register (SFIDRFR) . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 3-32. Sync Frame ID Acceptance Filter Value Register (SFIDAFVR). . . . . . . . . . . . . . . . . . 103
Figure 3-33. Sync Frame ID Acceptance Filter Mask Register (SFIDAFMR). . . . . . . . . . . . . . . . . . 103
Figure 3-34. Network Management Vector Registers (NMVR0–NMVR5) . . . . . . . . . . . . . . . . . . . . 103
Figure 3-35. Network Management Vector Length Register (NMVLR) . . . . . . . . . . . . . . . . . . . . . . 104
Figure 3-36. Timer Configuration and Control Register (TICCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 3-37. Timer 1 Cycle Set Register (TI1CYSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 3-38. Timer 1 Macrotick Offset Register (TI1MTOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 3-39. Timer 2 Configuration Register 0 (TI2CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 3-40. Timer 2 Configuration Register 1 (TI2CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 3-41. Slot Status Selection Register (SSSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 3-42. Slot Status Counter Condition Register (SSCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 3-43. Slot Status Registers (SSR0–SSR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 3-44. Slow Status Counter Registers (SSCR0–SSCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 3-45. MTS A Configuration Register (MTSACFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 3-46. MTS B Configuration Register (MTSBCFR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 3-47. Receive Shadow Buffer Index Register (RSBIR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 3-48. Receive FIFO Selection Register (RFSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 3-49. Receive FIFO Start Index Register (RFSIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 3-50. Receive FIFO Depth and Size Register (RFDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 3-51. Receive FIFO A Read Index Register (RFARIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 3-52. Receive FIFO B Read Index Register (RFBRIR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 3-53. Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR). . . . . . . 117
Figure 3-54. Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR) . . . . . . . . 118
Figure 3-55. Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR). . . . . . . . . . . 118
Figure 3-56. Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR). . . . . . . . . . . 118