FlexRay Module (FLEXRAYV4)
MFR4310 Reference Manual, Rev. 2
198 Freescale Semiconductor
3.4.19.1.2 Receive FIFO Interrupts
The FlexRay module provides 2 Receive FIFO interrupt sources.
Each of the 2 Receive FIFO provides a Receive FIFO Not Empty Interrupt Flag. The FlexRay module sets
the Receive FIFO Not Empty Interrupt Flags (GIFER.FNEBIF, GIFER.FNEAIF) in the Global Interrupt
Flag and Enable Register (GIFER) if the corresponding Receive FIFO is not empty.
3.4.19.1.3 Wakeup Interrupt
The FlexRay module provides one interrupt source related to the wakeup.
The FlexRay module sets the Wakeup Interrupt Flag GIFER.WUPIF when it has received a wakeup
symbol on the FlexRay bus. The FlexRay module generates an interrupt request if the interrupt enable bit
GIFER.WUPIE is asserted.
3.4.19.1.4 Protocol Interrupts
The FlexRay module provides 25 interrupt sources for protocol related events. For details, see Protocol
Interrupt Flag Register 0 (PIFR0) and Protocol Interrupt Flag Register 1 (PIFR1). Each interrupt source
has its own interrupt enable bit.
3.4.19.1.5 CHI Error Interrupts
The FlexRay module provides 16 interrupt sources for CHI related error events. For details, see CHI Error
Flag Register (CHIERFR). There is one common interrupt enable bit GIFER.CHIIE for all CHI error
interrupt sources.
3.4.19.2 Combined Interrupt Sources
Each combined interrupt source generates an interrupt request only when at least one of the interrupt
sources that is combined generates an interrupt request.
3.4.19.2.1 Receive Message Buffer Interrupt
The combined receive message buffer interrupt request RBIRQ is generated when at least one of the
individual receive message buffers generates an interrupt request MBXIRQ[n] and the interrupt enable bit
GIFER.RBIE is set.
3.4.19.2.2 Transmit Message Buffer Interrupt
The combined transmit message buffer interrupt request TBIRQ is generated when at least one of the
individual transmit message buffers generates an interrupt request MBXIRQ[n] and the interrupt enable
bit GIFER.TBIE is asserted.
3.4.19.2.3 Protocol Interrupt
The combined protocol interrupt request PRTIRQ is generated when at least one of the individual protocol
interrupt sources generates an interrupt request and the interrupt enable bit GIFER.PRIE is set.
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