MFR4310 Reference Manual, Rev. 2
Freescale Semiconductor 263
Appendix D
Index of Registers
A
ASIC Version Number Register (AVNR) 210
D
Channel A Status Error Counter Register (CASERCR) 89
Channel B Status Error Counter Register (CBSERCR) 89
CHI Error Flag Register (CHIERFR) 86
Clock and Reset Status Register (CRSR) 225
Combined Interrupt Flag Register (CIFRR) 98
Cycle Counter Register (CYCTR) 96
D
Detection Enable Register (DER) 224
G
Global Interrupt Flag and Enable Register (GIFER) 78
H
Host Interface Pins Drive Strength Register (HIPDSR) 210
Host Interface Pins Pullup/down Control Register (HIPPCR) 213
Host Interface Pins Pullup/down Enable Register (HIPPER) 212
L
Last Dynamic Transmit Slot Channel A Register (LDTXSLAR) 120
Last Dynamic Transmit Slot Channel B Register (LDTXSLBR) 121
M
Macrotick Counter Register (MTCTR) 96
Message Buffer Configuration, Control, Status Registers (MBCCSRn) 130
Message Buffer Cycle Counter Filter Registers (MBCCFRn) 132
Message Buffer Data Size Register (MBDSR) 75
Message Buffer Frame ID Registers (MBFIDRn) 133
Message Buffer Index Registers (MBIDXRn) 133
Message Buffer Interrupt Vector Register (MBIVEC) 88