Device Overview
MFR4310 Reference Manual, Rev. 2
30 Freescale Semiconductor
• Two independent receive FIFOs
— One receive FIFO per channel
— Up to 256 entries for each FIFO
— Global frame ID filtering, based on both value/mask filters and range filters
— Global channel ID filtering
— Global message ID filtering for the dynamic segment
• Four configurable slot error counters
• Four dedicated slot status indicators
— Used to observe slots without using receive message buffers
• Provides measured value indicators for clock synchronization
— PE internal synchronization frame ID and measurement tables can be copied into the FlexRay
memory
• Fractional macroticks are supported for clock correction
• Maskable interrupt sources provided through individual and combined interrupt lines
• One absolute timer
• One timer that can be configured to absolute or relative
Features specific to the MFR4310 include the following:
• Identical pinout to MFR4300; pin functionality compatible with MFR4300
• Three hardware selectable host interfaces:
— HCS12 Interface for direct connection to Freescale’s HCS12 family of microcontrollers, with
interface clock signal to synchronize the data transfer (the maximum frequency of this clock
signal can be calculated from the ECLK_CC pulse width low and high times, t
LEC
and t
HEC
given in Table A-15.)
— Asynchronous Memory Interface (AMI) for asynchronous connection to microcontrollers —
minimum read access time of 56 ns (with CHICLK_CC running at 76 MHz)
— MPC Interface for asynchronous connection to Freescale’s MPC5xx and MPC55xx family
microcontrollers — minimum read access time of 56 ns (with CHICLK_CC running at
76 MHz)
• 8K bytes addressable for byte or word accesses
• Internal quartz oscillator of 40 MHz
• CHI and AMI/MPC clock selectable between 40 MHz oscillator clock used for PE and 20 MHz to
76 MHz separate CHI/AMI/MPC-only clock
• Internal voltage regulator for the digital logic and the oscillator
• Hardware selectable clock output to drive external host devices: disabled, 4, 10, or 40 MHz
• Maskable interrupt sources available over one interrupt output line
• RESET# glitch filter
• Electrical physical layer interface compatible with dedicated FlexRay physical layer
• Four multiplexed debug strobe pins
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