Device Overview
MFR4310 Reference Manual, Rev. 2
42 Freescale Semiconductor
2.4.3.15 CLKOUT — Clock Output
CLKOUT is a continuous clock output signal. The frequency of CLKOUT is selected by the CLK_S[1:0]
pins. The CLKOUT signal, if enabled, is always active:
1. after power-up of the CC,
2. after a low-voltage reset,
3. after a clock monitor failure reset,
4. during and after an external hard reset.
The pin can be configured to provide high or reduced output drive.
NOTE
As the CLKOUT signal can be disabled during internal resets, refer to
Section 6.4.3, “CLKOUT Mode Selection and Control” for more
information on CLKOUT generation during external hard and internal
resets.
2.4.3.16 RESET# — External Reset
RESET# is an active-low control signal that acts as an input to initialize the CC to a known startup state.
The RESET# pin is pulled down internally.
NOTE
The CRG has a built-in RESET# glitch filter to prevent glitches on the
RESET# pin from resetting the device (see Section 6.4.1.4, “RESET#
Glitch Filter”).
2.4.3.17 INT_CC# — Interrupt Output
INT_CC# is an AMI/MPC and HCS12 interfaces interrupt request output signal. The CC may request a
service routine from the host to run. The interrupt is indicated by the logic level: the interrupt is asserted
if the INT_CC# outputs a logic 0 and is deasserted if INT_CC# outputs a logic 1.
The pin can be configured to provide high or reduced output drive. This is an open-drain output.
2.4.3.18 TEST
The TEST pin is pulled down, internally, and must be tied to VSS in all applications.
2.4.3.19 DBG[3:2]/CLK_S[1:0] — Debug Strobe Points, Output Clock Select
DBG[3:2] are debug strobe point output signals. The functions output on these pins are selected by the
debug port control register. Refer to Section 3.4.16, “Strobe Signal Support” for more information.
NOTE
CLK_S[1:0] signals are inputs during the internal reset sequence and are
latched during the internal reset sequence.
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