S/5
TM
UPINET Board, B-UPI4NET-02
3
Document no. M1137269-02
2 Functional description
2.1 General
2.1.1 UPI4NET board, B-UPI4NET
The UPI section functions as a general I/O-board. It performs I/O duties assigned to it by the
CPU board. The main processor in the CPU board and the processor in the UPI section
communicate through a dual-port memory which is located on the UPI4NET board.
Functional blocks
The UPI section contains the external bus interface, a processor, program and dual-port
memories and I/O-block.
Figure 2 UPI section block diagram
External bus interface
The UPI section is connected to the CPU mother board. The following signals pass on between
the UPI section and CPU mother board: data bus, address bus, reset, read and write signals,
and other related signals.
Processor
The processor in the UPI section is an H8S/2655, which functions at 16 MHz frequency.
RS232 serial bus interfaces
RS232 serial bus is connected to the connector X8. That serial channel is driven by the CPU
board. Only the RS232 buffer and some filtering components are located in the UPI4NET board.
RS485 module bus interface
RS485 half-duplex communication bus for modules. Communication speed rate is 500 kbps.
PLD
UPI CPU
RAM
JTAG
PLD EPROM
DIS bus
X5
S5 module bus
Temperature
and voltage
measuremants
S5 CPU BUS (X1 96-pin)
UPI
ID EEPROM
LPT-port
X3
RS232
Serial bus
X8
SyncOut
X7
UPI section upi4net-02 blck dgrm vsd
Location ID
connector
X4
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