Hioki 3153 - Page 165

152
_____________________________________________________________________________________________
9.1 External I/O Terminal
______________________________________________________________________________________________
H.V.ON
―――――――
READY
―――――――
TEST
――――――
STOP
――――――
50 ms
min.
210 ms max.
Voltage Output
H.V.ON
―――――――
READY
―――――――
TEST
――――――
STOP
――――――
50 ms
min.
200 ms max.
Voltage Output
(3) Timing chart at forced termination
When the
STOP
key is pressed to forcibly terminate testing, the unit does not
change to either PASS or FAIL status, as test screening is not performed. In
this case, the signal becomes HIGH level. In the absence of status indicators
(READY/TEST/FAIL/PASS) -- in the SETTING state, when set values are
being saved or loaded, or when settings are being made for the optional
functions -- all signals become HIGH level.
Withstand-voltage mode (when the hold function is not used)
Insulation-resistance mode (when the hold function is not used)