EasyManua.ls Logo

Schweitzer Engineering Laboratories SEL-311C - Page 343

Schweitzer Engineering Laboratories SEL-311C
748 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Date _______________
Date Code 20060320 Instruction Manual SEL-311C Relay
SET.13 of 32Settings Sheets for the SEL-311C Relay
Relay Settings (Serial Port Command SET and Front Panel)
POTT Trip Scheme Settings (Also Used in DCUB Trip Schemes) (See Figure 5.6)
(Make the following settings if preceding enable setting ECOMM = POTT, DCUB1, or DCUB2.)
Zone (level) 3 reverse block time delay
(0.00–16000.00 cycles in 0.25-cycle steps)
Z3RBD =
Echo block time delay
(OFF, 0.00–16000.00 cycles in 0.25-cycle steps)
EBLKD =
Echo time delay pickup
(OFF, 0.00–16000.00 cycles in 0.25-cycle steps)
ETDPU =
Echo duration time delay
(0.00–16000.00 cycles in 0.25-cycle steps)
EDURD =
Weak-infeed enable (Y, N)
EWFC =
WIF phase-to-phase undervoltage (0.0–260.0 V secondary)
27PPW =
WIF zero-sequence (3V0) overvoltage (0.0–150.0 V secondary)
59NW =
Additional DCUB Trip Scheme Settings (See Figure 5.10)
(Make the following settings if preceding enable setting ECOMM = DCUB1 or DCUB2.)
Guard present security time delay
(0.00–16000.00 cycles in 0.25-cycle steps)
GARD1D =
DCUB disabling time delay
(0.25–16000.00 cycles in 0.25-cycle steps)
UBDURD =
DCUB duration time delay
(0.00–16000.00 cycles in 0.25-cycle steps)
UBEND =
Channel A MIRRORED BITS Settings
(These settings are available when a Serial Port Protocol Setting has been set to MBGA.)
Channel A M
IRRORED BITS Enable (Y, N) EMBA =
Channel A M
IRRORED BITS Receive ID (1–4) RXIDA =
Channel A M
IRRORED BITS Transmit ID (1–4) TXIDA =
Channel B MIRRORED BITS Settings
(These settings are available when a Serial Port Protocol Setting has been set to MBGB.)
Channel B M
IRRORED BITS Enable (Y, N) EMBB =
Channel B M
IRRORED BITS Receive ID (1–4) RXIDB =
Channel B M
IRRORED BITS Transmit ID (1–4) TXIDB =
DCB Trip Scheme Settings (See Figure 5.14)
(Make the following settings if preceding enable setting ECOMM = DCB.)
Zone (level) 3 reverse pickup time delay
(0.00–16000.00 cycles in 0.25-cycle steps)
Z3XPU =

Table of Contents