DocID13902 Rev 15 1000/1128
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller
1064
PTP pulse-per-second output signal
This PTP pulse output is used to check the synchronization between all nodes in the
network. To be able to test the difference between the local slave clock and the master
reference clock, both clocks were given a pulse-per-second (PPS) output signal that may be
connected to an oscilloscope if necessary. The deviation between the two signals can
therefore be measured. The pulse width of the PPS output is 125 ms.
The PPS output is enabled through bit 30 in the AFIO_MAPR register.
Figure 351. PPS output
29.6 Ethernet functional description: DMA controller operation
The DMA has independent transmit and receive engines, and a CSR space. The transmit
engine transfers data from system memory into the Tx FIFO while the receive engine
transfers data from the Rx FIFO into system memory. The controller utilizes descriptors to
efficiently move data from source to destination with minimum CPU intervention. The DMA
is designed for packet-oriented data transfers such as frames in Ethernet. The controller can
be programmed to interrupt the CPU in cases such as frame transmit and receive transfer
completion, and other normal/error conditions. The DMA and the STM32F107xx
communicate through two data structures:
• Control and status registers (CSR)
• Descriptor lists and data buffers.
Control and status registers are described in detail in Section 29.8 on page 1022.
Descriptors are described in detail in Section on page 1008.
The DMA transfers the received data frames to the receive buffer in the
STM32F107xxmemory, and transmits data frames from the transmit buffer in the
STM32F107xx memory. Descriptors that reside in the STM32F107xx memory act as
pointers to these buffers. There are two descriptor lists: one for reception, and one for
transmission. The base address of each list is written into DMA Registers 3 and 4,
respectively. A descriptor list is forward-linked (either implicitly or explicitly). The last
descriptor may point back to the first entry to create a ring structure. Explicit chaining of
descriptors is accomplished by configuring the second address chained in both the receive
and transmit descriptors (RDES1[14] and TDES0[20]). The descriptor lists reside in the
Host’s physical memory space. Each descriptor can point to a maximum of two buffers. This
enables the use of two physically addressed buffers, instead of two contiguous buffers in
memory. A data buffer resides in the Host’s physical memory space, and consists of an
entire frame or part of a frame, but cannot exceed a single frame. Buffers contain only data.
The buffer status is maintained in the descriptor. Data chaining refers to frames that span
multiple data buffers. However, a single descriptor cannot span multiple frames. The DMA
skips to the next frame buffer when the end of frame is detected. Data chaining can be
enabled or disabled. The descriptor ring and chain structure is shown in Figure 352.
Ethernet MAC
ai15672
PPS output
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