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ST STM32F101 series Reference Manual

ST STM32F101 series
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Inter-integrated circuit (I
2
C) interface RM0008
769/1128 DocID13902 Rev 15
26.6.3 I
2
C Own address register 1 (I2C_OAR1)
Address offset: 0x08
Reset value: 0x0000
26.6.4 I
2
C Own address register 2 (I2C_OAR2)
Address offset: 0x0C
Reset value: 0x0000
15141312111098 7 654321 0
ADD
MODE
Reserved
ADD[9:8] ADD[7:1] ADD0
rw rw rw rw rw rw rw rw rw rw rw
Bit 15 ADDMODE Addressing mode (slave mode)
0: 7-bit slave address (10-bit address not acknowledged)
1: 10-bit slave address (7-bit address not acknowledged)
Bit 14 Should always be kept at 1 by software.
Bits 13:10 Reserved, must be kept at reset value
Bits 9:8 ADD[9:8]: Interface address
7-bit addressing mode: don’t care
10-bit addressing mode: bits9:8 of address
Bits 7:1 ADD[7:1]: Interface address
bits 7:1 of address
Bit 0 ADD0: Interface address
7-bit addressing mode: don’t care
10-bit addressing mode: bit 0 of address
151413121110987 654321 0
Reserved
ADD2[7:1] ENDUAL
rw rw rw rw rw rw rw rw
Bits 15:8 Reserved, must be kept at reset value
Bits 7:1 ADD2[7:1]: Interface address
bits 7:1 of address in dual addressing mode
Bit 0 ENDUAL: Dual addressing mode enable
0: Only OAR1 is recognized in 7-bit addressing mode
1: Both OAR1 and OAR2 are recognized in 7-bit addressing mode

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ST STM32F101 series Specifications

General IconGeneral
BrandST
ModelSTM32F101 series
CategoryComputer Hardware
LanguageEnglish

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