Debug support (DBG) RM0008
1099/1128 DocID13902 Rev 15
31.17.10 Example of configuration
• Set the bit TRCENA in the Debug Exception and Monitor Control Register (DEMCR)
• Write the TPIU Current Port Size Register to the desired value (default is 0x1 for a 1-bit
port size)
• Write TPIU Formatter and Flush Control Register to 0x102 (default value)
• Write the TPIU Select Pin Protocol to select the sync or async mode. Example: 0x2 for
async NRZ mode (UART like)
• Write the DBGMCU control register to 0x20 (bit IO_TRACEN) to assign TRACE I/Os
for async mode. A TPIU Sync packet is emitted at this time (FF_FF_FF_7F)
• Configure the ITM and write the ITM Stimulus register to output a value
0xE0040304
Formatter and flush
control
Bit 31-9 = always ‘0
Bit 8 = TrigIn = always ‘1 to indicate that triggers are indicated
Bit 7-4 = always 0
Bit 3-2 = always 0
Bit 1 = EnFCont. In Sync Trace mode (Select_Pin_Protocol register
bit1:0=00), this bit is forced to ‘1: the formatter is automatically enabled
in continuous mode. In asynchronous mode (Select_Pin_Protocol
register bit1:0 <> 00), this bit can be written to activate or not the
formatter.
Bit 0 = always 0
The resulting default value is 0x102
Note: In synchronous mode, because the TRACECTL pin is not mapped
outside the chip, the formatter is always enabled in continuous mode -this
way the formatter inserts some control packets to identify the source of
the trace packets).
0xE0040300
Formatter and flush
status
Not used in Cortex
®
-M3, always read as 0x00000008
Table 233. Important TPIU registers (continued)
Address Register Description
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