ST STM32F101 series Reference Manual

DocID13902 Rev 15 740/1128
RM0008 Serial peripheral interface (SPI)
742
25.5.9 SPI_I
2
S prescaler register (SPI_I2SPR)
Address offset: 0x20
Reset value: 0000 0010 (0x0002)
Bits 5:4 I2SSTD: I2S standard selection
00: I
2
S Philips standard.
01: MSB justified standard (left justified)
10: LSB justified standard (right justified)
11: PCM standard
For more details on I
2
S standards, refer to Section 25.4.2 on page 715. Not used in SPI mode.
Note: For correct operation, these bits should be configured when the I
2
S is disabled.
Bit 3 CKPOL: Steady state clock polarity
0: I
2
S clock steady state is low level
1: I
2
S clock steady state is high level
Note: For correct operation, this bit should be configured when the I
2
S is disabled.
This bit is not used in SPI mode
Bits 2:1 DATLEN: Data length to be transferred
00: 16-bit data length
01: 24-bit data length
10: 32-bit data length
11: Not allowed
Note: For correct operation, these bits should be configured when the I
2
S is disabled.
This bit is not used in SPI mode.
Bit 0 CHLEN: Channel length (number of bits per audio channel)
0: 16-bit wide
1: 32-bit wide
The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to
32-bit by hardware whatever the value filled in. Not used in SPI mode.
Note: For correct operation, this bit should be configured when the I
2
S is disabled.
1514131211109 876543210
Reserved
MCKOE ODD I2SDIV
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ST STM32F101 series Specifications

General

Brand	ST
Model	STM32F101 series
Category	Computer Hardware
Language	English