DocID13902 Rev 15 392/1128
RM0008 General-purpose timers (TIM2 to TIM5)
417
Using one timer to enable another timer
In this example, we control the enable of Timer 2 with the output compare 1 of Timer 1.
Refer to Figure 140 for connections. Timer 2 counts on the divided internal clock only when
OC1REF of Timer 1 is high. Both counter clock frequencies are divided by 3 by the
prescaler compared to CK_INT (f
CK_CNT
= f
CK_INT
/3).
• Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIM1_CR2 register).
• Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).
• Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR
register).
• Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).
• Enable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).
• Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).
Note: The counter 2 clock is not synchronized with counter 1, this mode only affects the Timer 2
counter enable signal.
Figure 141. Gating timer 2 with OC1REF of timer 1
In the example in Figure 141, the Timer 2 counter and prescaler are not initialized before
being started. So they start counting from their current value. It is possible to start from a
given value by resetting both timers before starting Timer 1. You can then write any value
you want in the timer counters. The timers can easily be reset by software using the UG bit
in the TIMx_EGR registers.
In the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts
from 0. Timer 2 is the slave and starts from 0xE7. The prescaler ratio is the same for both
TIMER 2-TIF
Write TIF=0
FC FD FE FF 00
3045 3047 3048
CK_INT
TIMER1-OC1REF
TIMER1-CNT
TIMER2-CNT
01
3046
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