Inter-integrated circuit (I
2
C) interface RM0008
755/1128 DocID13902 Rev 15
Figure 274. Method 2: transfer sequence diagram for master receiver when N>2
1. The EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence.
2. The EV7 software sequence must complete before the end of the current byte transfer.In case EV7
software sequence can not be managed before the current byte end of transfer, it is recommended to use
BTF instead of RXNE with the drawback of slowing the communication.
When 3 bytes remain to be read:
• RxNE = 1 => Nothing (DataN-2 not read).
• DataN-1 received
• BTF = 1 because both shift and data registers are full: DataN-2 in DR and DataN-1 in
the shift register => SCL tied low: no other data will be received on the bus.
• Clear ACK bit
• Read DataN-2 in DR => This will launch the DataN reception in the shift register
• DataN received (with a NACK)
• Program START/STOP
• Read DataN-1
• RxNE = 1
• Read DataN
AAddressS
EV5 EV6
AData1 AData2
EV7 EV7
ADataN-2 ADataN-1
EV7_2
NADataN
EV7
P
Legend: S = Start, S
r
= Repeated Start, P = Stop, A = Acknowledge, NA = Non-acknowledge,
EV5: SB=1, cleared by reading SR1 register followed by writing the DR register.
EV6: ADDR1, cleared by reading SR1 register followed by reading SR2.
In 10-bit master receiver mode, this sequence should be followed by writing CR2 with START = 1.
EV7: RxNE=1, cleared by reading DR register
EV7_2: BTF = 1, DataN-2 in DR and DataN-1 in shift register, program ACK = 0, Read DataN-2 in DR.
Program STOP = 1, read DataN-1.
7- bit master receiver
10- bit master receiver
AHeaderS
EV5 EV9
AData1 AData2
EV7 EV7
ADataN-2 ADataN-1
EV7_2
NADataN
EV7
P
AAddress
EV6
AHeaderS
r
EV5
EV6
EV9: ADD10= 1, cleared by reading SR1 register followed by writing DR register.
EVx = Event (with interrupt if ITEVFEN = 1)
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