ST STM32F101 series Reference Manual

Flexible static memory controller (FSMC) RM0008
511/1128 DocID13902 Rev 15
Mode A - SRAM/PSRAM (CRAM) OE toggling
Figure 189. ModeA read accesses
1. NBL[1:0] are driven low during read access.
Figure 190. ModeA write accesses
A[25:0]
NOE
(ADDSET +1) (DATAST + 1)
Memory transaction
Data strobe
NEx
D[15:0]
HCLK cycles HCLK cycles
NWE
NBL[1:0]
data driven
by memory
ai14722c
High
2 HCLK
cycles
Data sampled
A[25:0]
NOE
(ADDSET +1) (DATAST + 1)
Memory transaction
NEx
D[15:0]
HCLK cycles HCLK cycles
NWE
NBL[1:0]
data driven by FSMC
ai14721c
1HCLK

ST STM32F101 series Specifications

General

Brand	ST
Model	STM32F101 series
Category	Computer Hardware
Language	English