DocID13902 Rev 15 508/1128
RM0008 Flexible static memory controller (FSMC)
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21.5.3 General timing rules
Signals synchronization
• All controller output signals change on the rising edge of the internal clock (HCLK)
• In synchronous mode (read or write), all output signals change on the rising edge of
HCLK. Whatever the CLKDIV value, all outputs change as follows:
– NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the
falling edge of FSMC_CLK clock.
– NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising
edge of FSMC_CLK clock.
21.5.4 NOR Flash/PSRAM controller asynchronous transactions
Asynchronous static memories (NOR Flash memory, PSRAM, SRAM)
• Signals are synchronized by the internal clock HCLK. This clock is not issued to the
memory
• The FSMC always samples the data before de-asserting the chip select signal NE. This
guarantees that the memory data-hold timing constraint is met (chip enable high to
data transition, usually 0 ns min.)
• If the extended mode is enabled (EXTMOD bit is set in the FSMC_BCRx register), up
to four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and
D modes for read and write operations. For example, read operation can be performed
in mode A and write in mode B.
• If the extended mode is disabled (EXTMOD bit is reset in the FSMC_BCRx register),
the FSMC can operate in Mode1 or Mode2 as follows:
– Mode 1 is the default mode when SRAM/PSRAM memory type is selected (MTYP
= 0x0 or 0x01 in the FSMC_BCRx register)
– Mode 2 is the default mode when NOR memory type is selected (MTYP = 0x10 in
the FSMC_BCRx register).
Mode 1 - SRAM/PSRAM (CRAM)
The next figures show the read and write transactions for the supported modes followed by
the required configuration of FSMC _BCRx, and FSMC_BTRx/FSMC_BWTRx registers.
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