ST STM32F101 series Reference Manual

DocID13902 Rev 15 362/1128
RM0008 General-purpose timers (TIM2 to TIM5)
417
Figure 100. General-purpose timer block diagram
15.3 TIMx functional description
15.3.1 Time-base unit
The main block of the programmable timer is a 16-bit counter with its related auto-reload
register. The counter can count up, down or both up and down. The counter clock can be
divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
• Counter Register (TIMx_CNT)
• Prescaler Register (TIMx_PSC):
• Auto-Reload Register (TIMx_ARR)
Autoreload register
Capture/compare 1 register
Capture/compare 2 register
U
U
U
CC1I
CC2I
Trigger
controller
Stop, clear or up/down
TI1FP1
TI2FP2
ITR0
ITR1
ITR2
ITR3
TRGI
Encoder
Interface
Capture/compare 3 register
U
CC3I
output
control
OC1
TRGO
OC1REF
OC2REF
OC3REF
U
UI
Reset, enable, up/down, count,
Capture/compare 4 register
U
CC4I
OC4REF
Prescaler
Prescaler
IC4PS
IC3PS
IC1
IC2
Prescaler
Prescaler
Input filter &
edge detector
IC2PS
IC1PS
TI1FP1
OC2
OC3
OC4
Reg
event
Notes:
Preload registers transferred
to active registers on U event
according to control bit
interrupt & DMA output
TGI
TRC
TRC
IC3
IC4
ITR
TRC
TI1F_ED
Input filter &
edge detector
Input filter &
edge detector
Input filter &
edge detector
CC1I
CC2I
CC3I
CC4I
TI1FP2
TI2FP1
TI2FP2
TI3FP3
TRC
TRC
TI3FP4
TI4FP3
TI4FP4
TI4
TI3
TI1
TI2
XOR
TIMx_CH1
TIMx_CH2
TIMx_CH3
TIMx_CH4
TIMx_CH1
TIMx_CH2
TIMx_CH3
TIMx_CH4
to other timers
TIMxCLK from RCC
Prescaler counter
+/-
CK_PSC
PSC
CNT
CK_CNT
controller
mode
Slave
Internal Clock (CK_INT)
ETR
Input filter
Polarity selection & edge
detector & prescaler
ETRP
ETRF
TIMx_ETR
ETRF
to DAC/ADC
output
control
output
control
output
control

ST STM32F101 series Specifications

General

Brand	ST
Model	STM32F101 series
Category	Computer Hardware
Language	English