ST STM32F101 series Reference Manual

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RM0008 Connectivity line devices: reset and clock control (RCC)
158
8.3.5 APB1 peripheral reset register (RCC_APB1RSTR)
Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Bit 4 IOPCRST: IO port C reset
Set and cleared by software.
0: No effect
1: Reset I/O port C
Bit 3 IOPBRST: IO port B reset
Set and cleared by software.
0: No effect
1: Reset I/O port B
Bit 2 IOPARST: I/O port A reset
Set and cleared by software.
0: No effect
1: Reset I/O port A
Bit 1 Reserved, must be kept at reset value.
Bit 0 AFIORST: Alternate function I/O reset
Set and cleared by software.
0: No effect
1: Reset Alternate Function
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
DAC
RST
PWR
RST
BKP
RST
CAN2
RST
CAN1
RST
Reserved
I2C2
RST
I2C1
RST
UART5
RST
UART4
RST
USART
3
RST
USART
2
RST
Res.
rw rw rw rw rw rw rw rw rw rw rw
1514131211109 8 76543 2 1 0
SPI3
RST
SPI2
RST
Reserved
WWDG
RST
Reserved
TIM7
RST
TIM6
RST
TIM5
RST
TIM4
RST
TIM3
RST
TIM2
RST
rw rw rw rw rw rw rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACRST: DAC interface reset
Set and cleared by software.
0: No effect
1: Reset DAC interface
Bit 28 PWRRST: Power interface reset
Set and cleared by software.
0: No effect
1: Reset power interface
Bit 27 BKPRST: Backup interface reset
Set and cleared by software.
0: No effect
1: Reset backup interface

ST STM32F101 series Specifications

General

Brand	ST
Model	STM32F101 series
Category	Computer Hardware
Language	English