DocID13902 Rev 15 1110/1128
RM0008 Revision history
1120
22-Jun-
2009
9
Reference manual updated to support also STM32F105xx/STM32F107xx connectivity
line devices.
Memory and bus architecture section: Embedded boot loader updated.
Section 4.3: CRC functional description updated.
Note modified in Section 5.1.2: Battery backup domain.
Connectivity line devices: reset and clock control (RCC) section: Figure 10: Simplified
diagram of the reset circuit updated. PLL1 changed to PLL. Note added to BDP bit
description in Section 5.4.1: Power control register (PWR_CR). Table 57: SPI3/I2S3
remapping corrected.
DMA section: Table 76: Programmable data width & endian behavior (when bits PINC =
MINC = 1) updated, Section 13.3.1: DMA transactions and Pointer incrementation on
page 276 modified. DMA channel x peripheral address register (DMA_CPARx) (x =
1..7), where x = channel number) and DMA channel x memory address register
(DMA_CMARx) (x = 1..7), where x = channel number) must not be written when the
channel is enabled.
Advanced-control timer section: Section 14.3.12: Using the break function on page 318
updated. BKE and BKP bit descriptions updated in Section 14.4.18: TIM1&TIM8 break
and dead-time register (TIMx_BDTR). CC1IF bit description modified in Section 14.4.5:
TIM1&TIM8 status register (TIMx_SR) and Section 15.4.5: TIMx status register
(TIMx_SR).
Note added to Table 82: TIMx Internal trigger connection and Table 86: TIMx Internal
trigger connection on page 401.
Table 108: NOR Flash/PSRAM controller: example of supported memories and
transactions on page 507 and Single-burst transfer modified.
Register numbering and address offset corrected in Section 1.9.6: SDIO response 1..4
register (SDIO_RESPx) on page 646.
In Section 24: Controller area network (bxCAN): DBF bit reset value and access type
modified, small text changes.
SPI section: note added in Section 25.2.2: I2S features. Slave select (NSS) pin
management clarified. Note added at the end of Section 25.3.3: Configuring the SPI in
master mode and Section 25.3.4: Configuring the SPI for half-duplex communication.
Audio frequency precision tables 184 and 185 added to Section 25.4.3: Clock generator
on page 722 and audio sampling frequency range increased to 96 kHz.
Arbitration lost (ARLO) on page 758 specified.
USART section: Description of “1.5 stop bits” updated in Configurable stop bits, RTS
flow control corrected. Procedure sequence modified in Section 27.3.2: Transmitter.
How to derive USARTDIV from USART_BRR register values modified. Section 27.3.5:
USART receiver’s tolerance to clock deviation added. Section 27.3.11: Smartcard and
Section 27.3.10: Single-wire half-duplex communication updated. Bit 12 description
modified in Section 27.6.4: Control register 1 (USART_CR1).
Debug support (DBG) section:
– Figure 360: Block diagram of STM32 MCU and Cortex®-M3-level debug support
updated
– Section 31.15: ETM (Embedded trace macrocell) added
– Figure 363: TPIU block diagram updated
–in DBGMCU_IDCODE, REV_ID(15:0) updated for connectivity line devices (revision Z
added).
Section 28: USB on-the-go full-speed (OTG_FS) revised. Small text changes.
Table 235. Document revision history (continued)
Date Revision Changes
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