ST STM32F101 series Reference Manual

Revision history RM0008
1109/1128 DocID13902 Rev 15
11-Feb-
2009
8
Reset value corrected in Section 4.4.1: Data register (CRC_DR).
Section 11.10: Temperature sensor modified. Reset value corrected in Section 11.12.7:
ADC watchdog high threshold register (ADC_HTR).
Section 12.3.9: Triangle-wave generation and Figure 46: DAC triangle wave generation
updated.
Section 24.6: Debug mode added. Bit 16 updated in CAN master control register
(CAN_MCR) on page 665.
Note added to Section 25.3.6: CRC calculation.
Changes concerning the I
2
C peripheral (Inter-integrated circuit (I2C) interface):
–In Slave transmitter on page 747: text changes and Figure 270: Transfer sequence
diagram for slave transmitter modified.
–In Slave receiver on page 748: text changes and Figure 271: Transfer sequence
diagram for slave receiver modified.
– Master transmitter on page 751 and Master receiver on page 753 clarified.
–In Closing the communication on page 751: text changes and Figure 272: Transfer
sequence diagram for master transmitter modified.
– Figure 273: Method 1: transfer sequence diagram for master receiver modified.
– Overrun/underrun error (OVR) on page 758 clarified.
– Section 26.3.7: DMA requests and Section 26.3.8: Packet error checking updated.
–In Section 26.6.1: I2C Control register 1 (I2C_CR1): note modified under STOP bit
and notes modified under POS bit.
– Receiver mode modified in DR bit description in Section 26.6.5: I2C Data register
(I2C_DR).
– Note added to TxE and RxNE bit descriptions in Section 26.6.6: I2C Status register 1
(I2C_SR1).
Changes in FSMC section:
– Data setup and Address hold min values corrected in Table 104: Programmable
NOR/PSRAM access parameters.
– Memory wait min value corrected in Table 129: Programmable NAND/PC Card access
parameters.
– Bit descriptions modified in SRAM/NOR-Flash chip-select timing registers 1..4
(FSMC_BTR1..4) on page 535.
– DATAST and ADDHLD are reserved when equal to 0x0000 in SRAM/NOR-Flash chip-
select timing registers 1..4 (FSMC_BTR1..4) on page 535 and SRAM/NOR-Flash
write timing registers 1..4 (FSMC_BWTR1..4) on page 537.
– Bit descriptions modified in Common memory space timing register 2..4
(FSMC_PMEM2..4)
– ATTHOLDx and ATTWAITx bit descriptions modified in Attribute memory space timing
registers 2..4 (FSMC_PATT2..4)
– IOHOLDx bit description modified in I/O space timing register 4 (FSMC_PIO4)
Table 235. Document revision history (continued)
Date Revision Changes

ST STM32F101 series Specifications

General

Brand	ST
Model	STM32F101 series
Category	Computer Hardware
Language	English