Flexible static memory controller (FSMC) RM0008
551/1128 DocID13902 Rev 15
I/O space timing register 4 (FSMC_PIO4)
Address offset: 0xA000 0000 + 0xB0
Reset value: 0xFCFCFCFC
The FSMC_PIO4 read/write registers contain the timing information used to gain access to
the I/O space of the 16-bit PC Card/CompactFlash.
Bits 31:24 ATTHIZx: Attribute memory x databus HiZ time
Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
start of a PC CARD/NAND Flash write access to attribute memory space on socket x. Only
valid for write transaction:
0000 0000: 0 HCLK cycle
1111 1111: 255 HCLK cycles (default value after reset)
Bits 23:16 ATTHOLDx: Attribute memory x hold time
Defines the number of HCLK clock cycles to hold address (and data for write access) after
the command deassertion (NWE, NOE), for PC Card/NAND Flash read or write access to
attribute memory space on socket x
0000 0000: reserved
0000 0001: 1 HCLK cycle
1111 1111: 255 HCLK cycles (default value after reset)
Bits 15:8 ATTWAITx: Attribute memory x wait time
Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
NOE), for PC Card/NAND Flash read or write access to attribute memory space on socket x.
The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at
the end of the programmed value of HCLK:
0000 0000: reserved
0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)
(default value after reset)
Bits 7:0 ATTSETx: Attribute memory x setup time
Defines the number of HCLK (+1) clock cycles to set up address before the command
assertion (NWE, NOE), for PC CARD/NAND Flash read or write access to attribute memory
space on socket x:
0000 0000: 1 HCLK cycle
1111 1111: 256 HCLK cycles (default value after reset)
313029282726252423222120191817161514131211109876543210
IOHIZx IOHOLDx IOWAITx IOSETx
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