Independent watchdog (IWDG) RM0008
487/1128 DocID13902 Rev 15
The LSI can be calibrated so as to compute the IWDG timeout with an acceptable accuracy.
For more details refer to LSI clock on page 96.
19.4 IWDG registers
Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).
19.4.1 Key register (IWDG_KR)
Address offset: 0x00
Reset value: 0x0000 0000 (reset by Standby mode)
/128 5 3.2 13107.2
/256 6 (or 7) 6.4 26214.4
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Table 96. Min/max IWDG timeout period at 40 kHz (LSI)
(1)
(continued)
Prescaler divider PR[2:0] bits
Min timeout (ms) RL[11:0]=
0x000
Max timeout (ms) RL[11:0]=
0xFFF
313029282726252423222120191817161514131211109876543210
Reserved
KEY[15:0]
wwwwwww w wwwwwwww
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 KEY[15:0]: Key value (write only, read 0000h)
These bits must be written by software at regular intervals with the key value AAAAh,
otherwise the watchdog generates a reset when the counter reaches 0.
Writing the key value 5555h to enable access to the IWDG_PR and IWDG_RLR registers
(see Section 19.3.2)
Writing the key value CCCCh starts the watchdog (except if the hardware watchdog option is
selected)
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