DocID13902 Rev 15 848/1128
RM0008 USB on-the-go full-speed (OTG_FS)
957
Device-mode CSR map
These registers must be programmed every time the core changes to device mode.
OTG_FS_HCCHARx
0x500
0x520
...
0x6E0h
OTG_FS Host channel-x characteristics register (OTG_FS_HCCHARx)
(x = 0..7, where x = Channel_number) on page 878
OTG_FS_HCINTx 508h
OTG_FS Host channel-x interrupt register (OTG_FS_HCINTx) (x = 0..7,
where x = Channel_number) on page 879
OTG_FS_HCINTMSKx 50Ch
OTG_FS Host channel-x interrupt mask register (OTG_FS_HCINTMSKx)
(x = 0..7, where x = Channel_number) on page 880
OTG_FS_HCTSIZx 510h
OTG_FS Host channel-x transfer size register (OTG_FS_HCTSIZx)
(x = 0..7, where x = Channel_number) on page 881
Table 202. Host-mode control and status registers (CSRs) (continued)
Acronym
Offset
address
Register name
Table 203. Device-mode control and status registers
Acronym
Offset
address
Register name
OTG_FS_DCFG 0x800 OTG_FS device configuration register (OTG_FS_DCFG) on page 882
OTG_FS_DCTL 0x804 OTG_FS device control register (OTG_FS_DCTL) on page 883
OTG_FS_DSTS 0x808 OTG_FS device status register (OTG_FS_DSTS) on page 884
OTG_FS_DIEPMSK 0x810
OTG_FS device IN endpoint common interrupt mask register
(OTG_FS_DIEPMSK) on page 885
OTG_FS_DOEPMSK 0x814
OTG_FS device OUT endpoint common interrupt mask register
(OTG_FS_DOEPMSK) on page 886
OTG_FS_DAINT 0x818
OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) on
page 887
OTG_FS_DAINTMSK 0x81C
OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
on page 888
OTG_FS_DVBUSDIS 0x828
OTG_FS device VBUS discharge time register (OTG_FS_DVBUSDIS)
on page 888
OTG_FS_DVBUSPULS
E
0x82C
OTG_FS device VBUS pulsing time register (OTG_FS_DVBUSPULSE)
on page 889
OTG_FS_DIEPEMPMSK 0x834
OTG_FS device IN endpoint FIFO empty interrupt mask register:
(OTG_FS_DIEPEMPMSK) on page 889
OTG_FS_DIEPCTL0 0x900
OTG_FS device control IN endpoint 0 control register
(OTG_FS_DIEPCTL0) on page 890
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