ST STM32F101 series Reference Manual

DocID13902 Rev 15 776/1128
RM0008 Inter-integrated circuit (I
2
C) interface
777
26.6.9 I
2
C TRISE register (I2C_TRISE)
Address offset: 0x20
Reset value: 0x0002
Bit 14 DUTY: Fm mode duty cycle
0: Fm mode t
low
/t
high
= 2
1: Fm mode t
low
/t
high
= 16/9 (see CCR)
Bits 13:12 Reserved, must be kept at reset value
Bits 11:0 CCR[11:0]: Clock control register in Fm/Sm mode (Master mode)
Controls the SCL clock in master mode.
Sm mode or SMBus
:
T
high
= CCR * T
PCLK1
T
low
= CCR * T
PCLK1
Fm mode:
If DUTY = 0:
T
high
= CCR * T
PCLK1
T
low
= 2 * CCR * T
PCLK1
If DUTY = 1: (to reach 400 kHz)
T
high
= 9 * CCR * T
PCLK1
T
low
= 16 * CCR * T
PCLK1
For instance: in Sm mode, to generate a 100 kHz SCL frequency:
If FREQR = 08, T
PCLK1
= 125 ns so CCR must be programmed with 0x28
(0x28 <=> 40d x 125 ns = 5000 ns.)
Note: The minimum allowed value is 0x04, except in FAST DUTY mode where the minimum
allowed value is 0x01
t
high
= t
r(SCL)
+ t
w(SCLH)
. See device datasheet for the definitions of parameters.
t
low
= t
f(SCL)
+ t
w(SCLL)
. See device datasheet for the definitions of parameters.
I2C communication speed, fSCL ~ 1/(thigh + tlow). The real frequency may differ due to
the analog noise filter input delay.
The CCR register must be configured only when the I
2
C is disabled (PE = 0).
151413121110987 654321 0
Reserved
TRISE[5:0]
rw rw rw rw rw rw
Bits 15:6 Reserved, must be kept at reset value
Bits 5:0 TRISE[5:0]: Maximum rise time in Fm/Sm mode (Master mode)
These bits should provide the maximum duration of the SCL feedback loop in master mode.
The purpose is to keep a stable SCL frequency whatever the SCL rising edge duration.
These bits must be programmed with the maximum SCL rise time given in the I
2
C bus
specification, incremented by 1.
For instance: in Sm mode, the maximum allowed SCL rise time is 1000 ns.
If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 0x08 and T
PCLK1
= 125 ns
therefore the TRISE[5:0] bits must be programmed with 09h.
(1000 ns / 125 ns = 8 + 1)
The filter value can also be added to TRISE[5:0].
If the result is not an integer, TRISE[5:0] must be programmed with the integer part, in order
to respect the t
HIGH
parameter.
Note: TRISE[5:0] must be configured only when the I2C is disabled (PE = 0).

ST STM32F101 series Specifications

General

Brand	ST
Model	STM32F101 series
Category	Computer Hardware
Language	English