DocID13902 Rev 15 966/1128
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller
1064
29.4.2 Media-independent interface: MII
The media-independent interface (MII) defines the interconnection between the MAC
sublayer and the PHY for data transfer at 10 Mbit/s and 100 Mbit/s.
Figure 330. Media independent interface signals
• MII_TX_CLK: continuous clock that provides the timing reference for the TX data
transfer. The nominal frequency is: 2.5 MHz at 10 Mbit/s speed; 25 MHz at 100 Mbit/s
speed.
• MII_RX_CLK: continuous clock that provides the timing reference for the RX data
transfer. The nominal frequency is: 2.5 MHz at 10 Mbit/s speed; 25 MHz at 100 Mbit/s
speed.
• MII_TX_EN: transmission enable indicates that the MAC is presenting nibbles on the
MII for transmission. It must be asserted synchronously (MII_TX_CLK) with the first
nibble of the preamble and must remain asserted while all nibbles to be transmitted are
presented to the MII.
• MII_TXD[3:0]: transmit data is a bundle of 4 data signals driven synchronously by the
MAC sublayer and qualified (valid data) on the assertion of the MII_TX_EN signal.
MII_TXD[0] is the least significant bit, MII_TXD[3] is the most significant bit. While
MII_TX_EN is deasserted the transmit data must have no effect upon the PHY.
• MII_CRS: carrier sense is asserted by the PHY when either the transmit or receive
medium is non idle. It shall be deasserted by the PHY when both the transmit and
receive media are idle. The PHY must ensure that the MII_CS signal remains asserted
throughout the duration of a collision condition. This signal is not required to transition
synchronously with respect to the TX and RX clocks. In full duplex mode the state of
this signal is don’t care for the MAC sublayer.
• MII_COL: collision detection must be asserted by the PHY upon detection of a collision
on the medium and must remain asserted while the collision condition persists. This
signal is not required to transition synchronously with respect to the TX and RX clocks.
In full duplex mode the state of this signal is don’t care for the MAC sublayer.
• MII_RXD[3:0]: reception data is a bundle of 4 data signals driven synchronously by the
PHY and qualified (valid data) on the assertion of the MII_RX_DV signal. MII_RXD[0] is
the least significant bit, MII_RXD[3] is the most significant bit. While MII_RX_EN is
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