ST STM32F101 series Reference Manual

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RM0008 Independent watchdog (IWDG)
490
19.4.2 Prescaler register (IWDG_PR)
Address offset: 0x04
Reset value: 0x0000 0000
19.4.3 Reload register (IWDG_RLR)
Address offset: 0x08
Reset value: 0x0000 0FFF (reset by Standby mode)
19.4.4 Status register (IWDG_SR)
Address offset: 0x0C
313029282726252423222120191817161514131211109876543210
Reserved
PR[2:0]
rw rw rw
Bits 31:3 Reserved, must be kept at reset value.
Bits 2:0 PR[2:0]: Prescaler divider
These bits are write access protected seeSection 19.3.2. They are written by software to
select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in
order to be able to change the prescaler divider.
000: divider /4
001: divider /8
010: divider /16
011: divider /32
100: divider /64
101: divider /128
110: divider /256
111: divider /256
Note: Reading this register returns the prescaler value from the VDD voltage domain. This
value may not be up to date/valid if a write operation to this register is ongoing. For this
reason the value read from this register is valid only when the PVU bit in the IWDG_SR
register is reset.
313029282726252423222120191817161514131211109876543210
Reserved
RL[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:12 Reserved, must be kept at reset value.
Bits11:0 RL[11:0]: Watchdog counter reload value
These bits are write access protected see Section 19.3.2. They are written by software to
define the value to be loaded in the watchdog counter each time the value AAAAh is written
in the IWDG_KR register. The watchdog counter counts down from this value. The timeout
period is a function of this value and the clock prescaler. Refer to Table 96.
The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload
value.
Note: Reading this register returns the reload value from the VDD voltage domain. This value
may not be up to date/valid if a write operation to this register is ongoing on this
register. For this reason the value read from this register is valid only when the RVU bit
in the IWDG_SR register is reset.

ST STM32F101 series Specifications

General

Brand	ST
Model	STM32F101 series
Category	Computer Hardware
Language	English