ST STM32F101 series Reference Manual

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RM0008 Universal serial bus full-speed device interface (USB)
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23.5 USB registers
The USB peripheral registers can be divided into the following groups:
• Common Registers: Interrupt and Control registers
• Endpoint Registers: Endpoint configuration and status
• Buffer Descriptor Table: Location of packet memory used to locate data buffers
All register addresses are expressed as offsets with respect to the USB peripheral registers
base address 0x4000 5C00, except the buffer descriptor table locations, which starts at the
address specified by the USB_BTABLE register. Due to the common limitation of APB1
bridges on word addressability, all register addresses are aligned to 32-bit word boundaries
although they are 16-bit wide. The same address alignment is used to access packet buffer
memory locations, which are located starting from 0x4000 6000.
Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
23.5.1 Common registers
These registers affect the general behavior of the USB peripheral defining operating mode,
interrupt handling, device address and giving access to the current frame number updated
by the host PC.
USB control register (USB_CNTR)
Address offset: 0x40
Reset value: 0x0003
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTRM PMAOVRM ERRM WKUPM SUSPM RESETM SOFM ESOFM
Reserved
RESUME FSUSP LP_MODE PDWN FRES
rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 15 CTRM: Correct transfer interrupt mask
0: Correct Transfer (CTR) Interrupt disabled.
1: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the
USB_ISTR register is set.
Bit 14 PMAOVRM: Packet memory area over / underrun interrupt mask
0: PMAOVR Interrupt disabled.
1: PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit
in the USB_ISTR register is set.
Bit 13 ERRM: Error interrupt mask
0: ERR Interrupt disabled.
1: ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
Bit 12 WKUPM: Wakeup interrupt mask
0: WKUP Interrupt disabled.
1: WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.

ST STM32F101 series Specifications

General

Brand	ST
Model	STM32F101 series
Category	Computer Hardware
Language	English