ST STM32F101 series Reference Manual

Inter-integrated circuit (I
2
C) interface RM0008
775/1128 DocID13902 Rev 15
Note: Reading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was
set after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found
set in I2C_SR1 or when the STOPF bit is cleared.
26.6.8 I
2
C Clock control register (I2C_CCR)
Address offset: 0x1C
Reset value: 0x0000
Note: f
PCLK1
must be at least 2 MHz to achieve Sm mode I²C frequencies. It must be at least 4
MHz to achieve Fm mode I²C frequencies. It must be a multiple of 10MHz to reach the
400 kHz maximum I²C Fm mode clock.
The CCR register must be configured only when the I2C is disabled (PE = 0).
Bit 2 TRA: Transmitter/receiver
0: Data bytes received
1: Data bytes transmitted
This bit is set depending on the R/W bit of the address byte, at the end of total address
phase.
It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start
condition, loss of bus arbitration (ARLO=1), or when PE=0.
Bit 1 BUSY: Bus busy
0: No communication on the bus
1: Communication ongoing on the bus
– Set by hardware on detection of SDA or SCL low
– cleared by hardware on detection of a Stop condition.
It indicates a communication in progress on the bus. This information is still updated when
the interface is disabled (PE=0).
Bit 0 MSL: Master/slave
0: Slave Mode
1: Master Mode
– Set by hardware as soon as the interface is in Master mode (SB=1).
– Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration
(ARLO=1), or by hardware when PE=0.
151413121110987 654321 0
F/S DUTY
Reserved
CCR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 15 F/S: I2C master mode selection
0: Sm mode I2C
1: Fm mode I2C

ST STM32F101 series Specifications

General

Brand	ST
Model	STM32F101 series
Category	Computer Hardware
Language	English