ST STM32F101 series Reference Manual

DocID13902 Rev 15 654/1128
RM0008 Controller area network (bxCAN)
689
24.7.2 Time triggered communication mode
In this mode, the internal counter of the CAN hardware is activated and used to generate the
Time Stamp value stored in the CAN_RDTxR/CAN_TDTxR registers, respectively (for Rx
and Tx mailboxes). The internal counter is incremented each CAN bit time (refer to
Section 24.7.7: Bit timing). The internal counter is captured on the sample point of the Start
Of Frame bit in both reception and transmission.
24.7.3 Reception handling
For the reception of CAN messages, three mailboxes organized as a FIFO are provided. In
order to save CPU load, simplify the software and guarantee data consistency, the FIFO is
managed completely by hardware. The application accesses the messages stored in the
FIFO through the FIFO output mailbox.
Valid message
A received message is considered as valid when it has been received correctly according to
the CAN protocol (no error until the last but one bit of the EOF field) and It passed through
the identifier filtering successfully, see Section 24.7.4: Identifier filtering.
Figure 228. Receive FIFO states
EMPTY
Valid Message
FMP=0x00
FOVR=0
PENDING_1
FMP=0x01
FOVR=0
Received
PENDING_2
FMP=0x10
FOVR=0
PENDING_3
FMP=0x11
FOVR=0
Valid Message
Received
Release
OVERRUN
FMP=0x11
FOVR=1
Mailbox
Release
Mailbox
Valid Message
Received
Valid Message
Received
Release
Mailbox
Release
Mailbox
Valid Message
Received
RFOM=1
RFOM=1
RFOM=1

ST STM32F101 series Specifications

General

Brand	ST
Model	STM32F101 series
Category	Computer Hardware
Language	English