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Basic timers (TIM6&TIM7) RM0008

463/1128 DocID13902 Rev 15

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It

is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).

It can be changed on the fly as the TIMx_PSC control register is buffered. The new

prescaler ratio is taken into account at the next update event.

Figure 170 and Figure 171 give some examples of the counter behavior when the prescaler

ratio is changed on the fly.

Figure 170. Counter timing diagram with prescaler division change from 1 to 2

Figure 171. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CNT_EN

Timer clock = CK_CNT

Counter register

Update event (UEV)

F9 FA FB FCF7

Prescaler control register

Write a new value in TIMx_PSC

01 02 03

Prescaler buffer

Prescaler counter

1 0 1 0 1 0 1