DocID13902 Rev 15 524/1128
RM0008 Flexible static memory controller (FSMC)
555
1. Memory asserts the WAIT signal aligned to NOE/NWE which toggles:
2. Memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
if
then
otherwise
where max_wait_assertion_time is the maximum time taken by the memory to assert
the WAIT signal once NEx/NOE/NWE is low.
Figure 199 and Figure 200 show the number of HCLK clock cycles that are added to the
memory access after WAIT is released by the asynchronous memory (independently of the
above cases).
Figure 199. Asynchronous wait during a read access
1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.
DATAST 4 HCLK×()max_wait_assertion_time+≥
max_wait_assertion_time address_phase hold_phase+>
DATAST 4 HCLK×()max_wait_assertion_time address_phase– hold_phase–()+≥
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