ST STM32F101 series Reference Manual

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RM0008 Connectivity line devices: reset and clock control (RCC)
158
8.3.12 Clock configuration register2 (RCC_CFGR2)
Address offset: 0x2C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
7
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
I2S3SR
C
I2S2SR
C
PREDIV
1SRC
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL3MUL[3:0] PLL2MUL[3:0] PREDIV2[3:0] PREDIV1[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 I2S3SRC: I2S3 clock source
Set and cleared by software to select I2S3 clock source. This bit must be valid before
enabling I2S3 clock.
0: System clock (SYSCLK) selected as I2S3 clock entry
1: PLL3 VCO clock selected as I2S3 clock entry
Bit 17 I2S2SRC: I2S2 clock source
Set and cleared by software to select I2S2 clock source. This bit must be valid before
enabling I2S2 clock.
0: System clock (SYSCLK) selected as I2S2 clock entry
1: PLL3 VCO clock selected as I2S2 clock entry
Bit 16 PREDIV1SRC: PREDIV1 entry clock source
Set and cleared by software to select PREDIV1 clock source. This bit can be written only
when PLL is disabled.
0: HSE oscillator clock selected as PREDIV1 clock entry
1: PLL2 selected as PREDIV1 clock entry
Bits 15:12 PLL3MUL[3:0]: PLL3 Multiplication Factor
Set and cleared by software to control PLL3 multiplication factor. These bits can be written
only when PLL3 is disabled.
00xx: Reserved
010x: Reserved
0110: PLL3 clock entry x 8
0111: PLL3 clock entry x 9
1000: PLL3 clock entry x 10
1001: PLL3 clock entry x 11
1010: PLL3 clock entry x 12
1011: PLL3 clock entry x 13
1100: PLL3 clock entry x 14
1101: Reserved
1110: PLL3 clock entry x 16
1111: PLL3 clock entry x 20

ST STM32F101 series Specifications

General

Brand	ST
Model	STM32F101 series
Category	Computer Hardware
Language	English