ST STM32F101 series Reference Manual

DocID13902 Rev 15 1108/1128
RM0008 Revision history
1120
23-Dec-
2008
7
Memory map figure removed from reference manual. Section 3.1: System architecture
on page 48 modified. Section 3.4: Boot configuration on page 61 modified. Exiting Sleep
mode on page 73 modified. Section 6.3.2: RTC calibration on page 82 updated. Wakeup
event management on page 206 updated.
Section 7.3: RCC registers on page 99 updated. Section 13.2: DMA main features on
page 273 updated.
Section 13.3.5: Error management modified. Figure 48: DMA block diagram in
connectivity line devices on page 274 modified. Section 13.3.4: Programmable data
width, data alignment and endians on page 278 added.
Bit definition modified in Section 13.4.5: DMA channel x peripheral address register
(DMA_CPARx) (x = 1..7), where x = channel number) on page 288 and Section 13.4.6:
DMA channel x memory address register (DMA_CMARx) (x = 1..7), where x = channel
number) on page 288.
Note added below Figure 82: PWM input mode timing and Figure 128: PWM input mode
timing.
FSMC_NWAIT signal direction corrected in Figure 185: FSMC block diagram on
page 500.
Value to set modified for bit 6 in Table 114: FSMC_BCRx bit fields, Table 11 7:
FSMC_BCRx bit fields and Table 123: FSMC_BCRx bit fields. Table 130: 8-bit NAND
Flash, Table 131: 16-bit NAND Flash and Table 132: 16-bit PC Card modified. NWAIT
and INTR signals separated in Table 132: 16-bit PC Card. Note added in PWAITEN bit
definition in PC Card/NAND Flash control registers 2..4 (FSMC_PCR2..4) on page 547.
Bit definitions updated in FIFO status and interrupt register 2..4 (FSMC_SR2..4) on
page 548. Note modified in ADDHLD and ADDSET bit definitions in SRAM/NOR-Flash
chip-select timing registers 1..4 (FSMC_BTR1..4) on page 535. Bit 8 is reserved in PC
Card/NAND Flash control registers 2..4 (FSMC_PCR2..4) on page 547.
MEMWAIT[15:8] bit definition modified in Common memory space timing register 2..4
(FSMC_PMEM2..4) on page 549.
ATTWAIT[15:8] bit definition modified in Attribute memory space timing registers 2..4
(FSMC_PATT2..4) on page 550.
Section 21.6.5: NAND Flash pre-wait functionality on page 543 modified. Figure 204:
NAND/PC Card controller timing for common memory access modified.
Note added below Table 100: NOR/PSRAM bank selection on page 502.
32-bit external memory access removed from
Table 101: External memory address on
page 503 and note added.
Caution: added to Section 21.6.1: External memory interface signals.
NIOS16 description modified in Table 132: 16-bit PC Card on page 540.
Register description modified in Attribute memory space timing registers 2..4
(FSMC_PATT2..4) on page 550.
Resetting the password on page 624 step 2 corrected.
write_data signal modified in Figure 204: NAND/PC Card controller timing for common
memory access.
bxCAN main features on page 645 modified.
Section 26.3.8: Packet error checking on page 763 modified.
Section 31.6.3: Cortex®-M3 TAP modified.
DBG_TIMx_STOP positions modified in DBGMCU_CR register on page 1091.
Small text changes.
Table 235. Document revision history (continued)
Date Revision Changes

ST STM32F101 series Specifications

General

Brand	ST
Model	STM32F101 series
Category	Computer Hardware
Language	English