ST STM32F101 series Reference Manual

DocID13902 Rev 15 1092/1128
RM0008 Debug support (DBG)
1100
DBGMCU_CR register
Address: 0xE004 2004
Only 32-bit access supported
POR Reset: 0x0000 0000 (not reset by system reset)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res.
DBG_
TIM11
_
STOP
DBG_
TIM10
_
STOP
DBG_
TIM9_
STOP
DBG_
TIM14
_
STOP
DBG_
TIM13
_
STOP
DBG_
TIM12_
STOP
Reserved
DGB_C
AN2_S
TOP
DBG_
TIM7_
STOP
DBG_
TIM6_
STOP
DBG_
TIM5_
STOP
DBG_
TIM8_
STOP
DBG_I2C2
_SMBUS_
TIMEOUT
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_I2C1
_SMBUS_
TIMEOUT
DBG_
CAN1
_
STOP
DBG_
TIM4_
STOP
DBG_
TIM3_
STOP
DBG_
TIM2_
STOP
DBG_
TIM1_
STOP
DBG_
WWDG
_
STOP
DBG_
IWDG
STOP
TRACE_
MODE
[1:0]
TRACE
_
IOEN
Reserved
DBG_
STAND
BY
DBG_
STOP
DBG_
SLEEP
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:25 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=9..14)
0: The clock of the involved timer counter is fed even if the core is halted, and the outputs
behave normally.
1: The clock of the involved timer counter is stopped when the core is halted, and the
outputs are disabled (as if there were an emergency stop in response to a break event).
Bits 24:22 Reserved, must be kept at reset value.
Bit 21 DBG_CAN2_STOP: Debug CAN2 stopped when core is halted
0: Same behavior as in normal mode
1: CAN2 receive registers are frozen
Bits 20:17 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=8..5)
0: The clock of the involved timer counter is fed even if the core is halted, and the outputs
behave normally.
1: The clock of the involved timer counter is stopped when the core is halted, and the
outputs are disabled (as if there were an emergency stop in response to a break event).
Bit 16 DBG_I2C2_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bit 15 DBG_I2C1_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bit 14 DBG_CAN1_STOP: Debug CAN1 stopped when Core is halted
0: Same behavior as in normal mode
1: CAN1 receive registers are frozen
Bits 12:11 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=4..1)
0: The clock of the involved Timer Counter is fed even if the core is halted
1: The clock of the involved Timer counter is stopped when the core is halted

ST STM32F101 series Specifications

General

Brand	ST
Model	STM32F101 series
Category	Computer Hardware
Language	English