Revision history RM0008
1107/1128 DocID13902 Rev 15
26-Sep-
2008
6
This reference manual also applies to low-density STM32F101xx, STM32F102xx and
STM32F103xx devices, and to medium-density STM32F102xx devices. In all sections,
definitions of low-density and medium-density devices updated.
Section 2.3: Peripheral availability on page 47 added.
Section 3.3.3: Embedded Flash memory on page 55 updated. Section 5.1.2: Battery
backup domain on page 69 modified. Reset value of Port input data register
(GPIOx_IDR) (x=A..G) on page 172 modified. Note added in Section 9.4: AFIO registers
on page 183. Note removed from bits 18:0 description in Section 10.3.6: Pending
register (EXTI_PR) on page 212.
Section 14.2: TIM1&TIM8 main features on page 293 and Section 15.2: TIMx main
features on page 361 updated. In Section 15.3.15: Timer synchronization on page 391,
TS=000.
FSMC_CLK signal direction corrected in Figure 185: FSMC block diagram on page 500.
“Feedback clock” paragraph removed from Section 21.5.3: General timing rules on
page 508.
In Section 21.5.6: NOR/PSRAM control registers on page 532: reset value modified,
WAITEN bit default value after reset is 1, bits [5:6] definition modified, , FACCEN default
value after reset specified. NWE signal behavior corrected in Figure 203: Synchronous
multiplexed write mode - PSRAM (CRAM) on page 530. The FSMC interface does not
support COSMO RAM and OneNAND devices, and it does not support the
asynchronous wait feature. SRAM and ROM 32 memory data size removed from
Table 108: NOR Flash/PSRAM controller: example of supported memories and
transactions on page 507.
Data latency versus NOR Flash latency on page 526 modified. Bits 19:16 bits are
reserved in SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) on
page 537.
Section 21.6.3: Timing diagrams for NAND and PC Card on page 541
modified.Definition of PWID bits modified in Section 21.6.8: NAND Flash/PC Card
control registers on page 547. Section 21.6.6: Computation of the error correction code
(ECC) in NAND Flash memory on page 544 modified.
Interrupt Mapper definition modified in Section 23.3.1: Description of USB blocks on
page 615. USB register and memory base addresses modified in Section 23.5: USB
registers on page 628.
Section 26.3.8: Packet error checking on page 763 modified.
Section : Start bit detection on page 787 added. PE bit description specified in Status
register (USART_SR) on page 811.
“RAM size register” section removed from Section 30: Device electronic signature on
page 1065. Bit definitions updated in FIFO status and interrupt register 2..4
(FSMC_SR2..4) on page 548.
Small text changes.
Table 235. Document revision history (continued)
Date Revision Changes
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