Flexible static memory controller (FSMC) RM0008
537/1128 DocID13902 Rev 15
SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4)
Address offset: 0xA000 0000 + 0x104 + 8 * (x – 1), x = 1...4
Reset value: 0x0FFF FFFF
This register contains the control information of each memory bank, used for SRAMs,
PSRAMs and NOR Flash memories. This register is active for write asynchronous access
only when the EXTMOD bit is set in the FSMC_BCRx register.
313029282726252423222120191817161514131211109876543210
Res.
ACCM
OD
Reserved
BUSTURN DATAST ADDHLD ADDSET
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:28 ACCMOD: Access mode.
Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are
taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1.
00: access mode A
01: access mode B
10: access mode C
11: access mode D
Bits 27:20 Reserved, must be kept at reset value.
Bits 19:16 BUSTURN: Bus turnaround phase duration
These bits are written by software to add a delay at the end of a write transaction to match the
minimum time between consecutive transactions (t
EHEL
from ENx high to ENx low):
(BUSTRUN + 1) HCLK period ≥ t
EHELmin
.
0000: BUSTURN phase duration = 1 HCLK clock cycle added
...
1111: BUSTURN phase duration = 16 HCLK clock cycles added (default value after reset)
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