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ST STM32F101 series Reference Manual

ST STM32F101 series
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DocID13902 Rev 15 1106/1128
RM0008 Revision history
1120
22-May-
2008
continued
4
continued
Figure 234: CAN frames on page 663 modified. Bits 31:21 and bits 20:3 modified in CAN
TX mailbox identifier register (CAN_TIxR) (x=0..2) on page 676. Bits 31:21 and bits 20:3
modified in CAN receive FIFO mailbox identifier register (CAN_RIxR) (x=0..1) on
page 679.
Section 26.3.7: DMA requests on page 761 modified. DMAEN bit 11 description
modified in Section 26.6.2: I2C Control register 2 (I2C_CR2) on page 767.
Clock phase and clock polarity on page 695 modified. Transmit sequence on page 697
modified. Receive sequence on page 698 added. Reception sequence on page 730
modified. Underrun flag (UDR) on page 731 modified.
I
2
S feature added (see Section 25: Serial peripheral interface (SPI) on page 690).
In Section 31: Debug support (DBG) on page 1068:
DBGMCU_IDCODE on page 1076 and DBGMCU_CR register on page 1091 updated
TMC TAP changed to boundary scan TAP
Address onto which DBGMCU_CR is mapped modified in Section 31.16.3: Debug
MCU configuration register on page 1091.
Section 30: Device electronic signature on page 1065 added.
REV_ID(15:0) definition modified in Section 31.6.1: MCU device ID code on page 1076.
28-Jul-2008 5
Developed polynomial form updated in Section 4.2: CRC main features on page 64.
Figure 4: Power supply overview on page 68 modified.
Section 5.1.2: Battery backup domain on page 69 modified.
Section 7.2.5: LSI clock on page 96 specified.
Section 9.1.4: Alternate functions (AF) on page 162 clarified.
Note added to Table 45: TIM2 alternate function remapping on page 179.
Bits are write-only in Section 13.4.2: DMA interrupt flag clear register (DMA_IFCR) on
page 285.
Register name modified in Section 11.3.1: ADC on-off control on page 218.
Recommended sampling time given in Section 11.10: Temperature sensor on page 234.
Bit attributes modified in Section 11.12.1: ADC status register (ADC_SR) on page 236.
Note modified for bits 23:0 in Section 11.12.4: ADC sample time register 1
(ADC_SMPR1) on page 243.
Note added in Section 12.2: DAC main features on page 253.
Formula updated in Section 12.3.5: DAC output voltage on page 257.
DBL[4:0] description modified in Section 14.3.19: TIMx and external trigger
synchronization on page 329.
Figure 82 on page 312 and Figure 128 on page 378 modified.
Section 25.5.3: SPI status register (SPI_SR) on page 736 modified.
Closing the communication on page 753 updated.
Notes added to Section 26.6.8: I2C Clock control register (I2C_CCR) on page 775. TCK
replaced by T
PCLK1
in Section 26.6.8 and Section 26.6.9.
OVR changed to ORE in Figure 301: USART interrupt mapping diagram on page 810.
Section 27.6.1: Status register (USART_SR) on page 811 updated.
Slave select (NSS) pin management on page 694 clarified.
Small text changes.
Table 235. Document revision history (continued)
Date Revision Changes

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ST STM32F101 series Specifications

General IconGeneral
BrandST
ModelSTM32F101 series
CategoryComputer Hardware
LanguageEnglish

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