Revision history RM0008
1105/1128 DocID13902 Rev 15
22-May-
2008
continued
4
(continued)
In Section 7: Low-, medium-, high- and XL-density reset and clock control (RCC) on
page 90:
– LSI calibration on page 97 added.
Figure 7: Simplified diagram of the reset circuit on page 91 updated
– APB2 peripheral reset register (RCC_APB2RSTR) on page 106 updated
– APB1 peripheral reset register (RCC_APB1RSTR) on page 109 updated
– AHB peripheral clock enable register (RCC_AHBENR) updated
– APB2 peripheral clock enable register (RCC_APB2ENR) updated
– APB1 peripheral clock enable register (RCC_APB1ENR) on page 115 updated (see
Section Table 18.: RCC register map and reset values).
– LSERDYIE definition modified in Clock interrupt register (RCC_CIR)
– HSITRIM[4:0] definition modified in Clock control register (RCC_CR)
In Section 9: General-purpose and alternate-function I/Os (GPIOs and AFIOs) on
page 159:
– GPIO ports F and G added
–In Section 9.3: Alternate function I/O and debug configuration (AFIO) on page 175
remapping for High-density devices added, note modified under Section 9.3.2,
Section 9.3.3 on page 176 modified
– AF remap and debug I/O configuration register (AFIO_MAPR) updated
Updated in Section 10: Interrupts and events on page 196:
– number of maskable interrupt channels
– number of GPIOs (see Figure 21: External interrupt/event GPIO mapping)
In Section 13: Direct memory access controller (DMA) on page 273:
– number of DMA controllers and configurable DMA channels updated
– Figure 48: DMA block diagram in connectivity line devices on page 274 updated,
notes added
– Note updated in Section 13.3.2: Arbiter on page 276.Note updated in Section 13.3.6:
Interrupts on page 280. Figure 50: DMA1 request mapping on page 281 updated
– DMA2 controller on page 282 added
In Section 11: Analog-to-digital converter (ADC) on page 214:
– ADC3 added (Figure 22: Single ADC block diagram on page 216 updated, Table 70:
External trigger for injected channels for ADC3 added, etc.). Section 12: Digital-to-
analog converter (DAC) on page 253 added.In Section 14: Advanced-control timers
(TIM1&TIM8) on page 292:
– Advanced control timer TIM8 added (see Figure 52: Advanced-control timer block
diagram on page 294
)
– TS[2:0] modified in Section 14.4.3: TIM1&TIM8 slave mode control register
(TIMx_SMCR) on page 337.
In Section 15: General-purpose timers (TIM2 to TIM5) on page 360:
– TIM5 added
– Figure 100: General-purpose timer block diagram updated. Table 86: TIMx Internal
trigger connection on page 401 modified. Section 17: Basic timers (TIM6&TIM7)
added.
– RTC clock sources specified in Section 18.2: RTC main features on page 474.
Section 18.1: RTC introduction modified.
Section 21: Flexible static memory controller (FSMC) on page 498 added.
Section 1: Secure digital input/output interface (SDIO) on page 602 added.
Table 235. Document revision history (continued)
Date Revision Changes
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