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DocID13902 Rev 15 768/1128

RM0008 Inter-integrated circuit (I

C) interface

777

Bit 9 ITEVTEN: Event interrupt enable

0: Event interrupt disabled

1: Event interrupt enabled

This interrupt is generated when:

– SB = 1 (Master)

– ADDR = 1 (Master/Slave)

– ADD10= 1 (Master)

– STOPF = 1 (Slave)

– BTF = 1 with no TxE or RxNE event

– TxE event to 1 if ITBUFEN = 1

– RxNE event to 1if ITBUFEN = 1

ITERREN: Error interrupt enable

0: Error interrupt disabled

1: Error interrupt enabled

This interrupt is generated when:

–BERR = 1

–ARLO = 1

–AF = 1

–OVR = 1

– PECERR = 1

–TIMEOUT = 1

– SMBALERT = 1

Bits 7:6 Reserved, must be kept at reset value

Bits 5:0 FREQ[5:0]: Peripheral clock frequency

The FREQ bits must be configured with the APB clock frequency value (I2C peripheral

connected to APB). The FREQ field is used by the peripheral to generate data setup and

hold times compliant with the I2C specifications. The minimum allowed frequency is 2 MHz,

the maximum frequency is limited by the maximum APB frequency (36 MHz) and an intrinsic

limitation of 46 MHz.

0b000000: Not allowed

0b000001: Not allowed

0b000010: 2 MHz

...

0b100100: 36 MHz

Higher than 0b100100: Not allowed

ST STM32F101 series Reference Manual

Other manuals for ST STM32F101 series