Revision history RM0008
1103/1128 DocID13902 Rev 15
20-Nov-
2007
2
Figure 278: USART block diagram modified.
Procedure modified in Character reception on page 788.
In Section 27.3.4: Fractional baud rate generation:
– Equation legend modified
– Table 192: Error calculation for programmed baud rates modified
– Note added
Small text changes. In CAN bit timing register (CAN_BTR) on page 674, bit 15 is
reserved.
Flash memory organization corrected, Table 5: Flash module organization (medium-
density devices) modified in Section 3.3.3: Embedded Flash memory.
Note added below Figure 4: Power supply overview in Section 5.1: Power supplies.
RTCSEL[1:0] bit description modified in Backup domain control register (RCC_BDCR).
Names of bits [0:2] corrected for RCC_APB1RSTR and RCC_APB1ENR in Table 18:
RCC register map and reset values.
Impedance value specified in A.4: Voltage glitch on ADC input 0 on page 500.
In Section 25.5.1: SPI control register 1 (SPI_CR1) (not used in I2S mode), BR[2:0]
description corrected.
Prescaler buffer behavior specified when an update event occurs (see Upcounting mode
on page 364, Downcounting mode on page 367 and Center-aligned mode (up/down
counting)).
AWDCH[4:0] modified in Section 11.12.2: ADC control register 1 (ADC_CR1) and bits
[26:24] are reserved in Section 11.12.4: ADC sample time register 1 (ADC_SMPR1).
CAN_BTR bit 8 is reserved in Table 181: bxCAN register map and reset values. CAN
master control register (CAN_MCR) on page 665 corrected.
V
REF+
range corrected in Table 65: ADC pins and in On 100-pin and 144-pin packages
on page 68.
Start condition on page 750 updated. Note removed in Table 34: CAN1 alternate
function remapping. Note added in Table 43: TIM4 alternate function remapping.
In Section 9.4.2: AF remap and debug I/O configuration register (AFIO_MAPR), bit
definition modified for USART2_REMAP = 0. In Section 9.4.3: External interrupt
configuration register 1 (AFIO_EXTICR1), bit definition modified for SPI1_REMAP = 0.
In Table 233: Important TPIU registers, at 0xE0040004, bit2 set is not supported.
TRACE port size setting corrected in TPUI TRACE pin assignment on page 1095.
Figure 13, Figure 15, Figure 16, Figure 17 and Figure 18 modified. Figure 14: Basic
structure of a five-volt tolerant I/O port bit added.
Table 9.3.1: Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 on
page 175 added.
Bit descriptions modified in Section 18.4.5 and Section 18.4.6.
JTAG ID code corrected in Section 31.7: JTAG debug port on page 1078
.
Modified: Section 20.2: WWDG main features, Section 6.2: BKP main features,
Section 6.3.1: Tamper detection, Section 6.3.2: RTC calibration, Section 23.3: USB
functional description, Controlling the downcounter, Section 5.1.2: Battery backup
domain, Section 8.2: Introduction.
ASOE bit description modified in Section 6.4.2: RTC clock calibration register
(BKP_RTCCR).
Table 235. Document revision history (continued)
Date Revision Changes
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